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/Linux-v6.1/arch/arm64/boot/dts/rockchip/
Drk3566-soquartz-cm4.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 /dts-v1/;
5 #include "rk3566-soquartz.dtsi"
8 model = "Pine64 RK3566 SoQuartz with CM4-IO Carrier Board";
9 compatible = "pine64,soquartz-cm4io", "pine64,soquartz", "rockchip,rk3566";
12 vcc12v_dcin: vcc12v-dcin-regulator {
13 compatible = "regulator-fixed";
14 regulator-name = "vcc12v_dcin";
15 regulator-always-on;
16 regulator-boot-on;
[all …]
Drk3566-soquartz.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 /dts-v1/;
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/pinctrl/rockchip.h>
21 stdout-path = "serial2:1500000n8";
24 gmac1_clkin: external-gmac1-clock {
25 compatible = "fixed-clock";
26 clock-frequency = <125000000>;
27 clock-output-names = "gmac1_clkin";
28 #clock-cells = <0>;
[all …]
Drk3568-bpi-r2-pro.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Author: Frank Wunderlich <frank-w@public-files.de>
7 /dts-v1/;
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/leds/common.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/soc/rockchip,vop2.h>
15 model = "Bananapi-R2 Pro (RK3568) DDR4 Board";
16 compatible = "rockchip,rk3568-bpi-r2pro", "rockchip,rk3568";
26 stdout-path = "serial2:1500000n8";
[all …]
/Linux-v6.1/Documentation/devicetree/bindings/sound/
Dwm8960.txt7 - compatible : "wlf,wm8960"
9 - reg : the I2C address of the device.
12 - wlf,shared-lrclk: This is a boolean property. If present, the LRCM bit of
16 When wm8960 works on synchronize mode and DACLRC pin is used to supply
18 DACLRC pin. If shared-lrclk is present, no need to enable DAC for captrue.
20 - wlf,capless: This is a boolean property. If present, OUT3 pin will be
24 - wlf,hp-cfg: A list of headphone jack detect configuration register values.
26 hp-cfg[0]: HPSEL[1:0] of R48 (Additional Control 4).
27 hp-cfg[1]: {HPSWEN:HPSWPOL} of R24 (Additional Control 2).
28 hp-cfg[2]: {TOCLKSEL:TOEN} of R23 (Additional Control 1).
[all …]
Dmt8195-afe-pcm.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/mt8195-afe-pcm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Trevor Wu <trevor.wu@mediatek.com>
14 const: mediatek,mt8195-audio
25 reset-names:
28 memory-region:
31 Shared memory region for AFE memif. A "shared-dma-pool".
32 See ../reserved-memory/reserved-memory.txt for details.
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/Linux-v6.1/sound/pci/hda/
Dhda_generic.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Generic BIOS auto-parser helper functions for HD-audio
13 /* table entry for multi-io paths */
15 hda_nid_t pin; /* multi-io widget pin NID */ member
17 unsigned int ctl_in; /* cached input-pin control value */
22 * For output, stored in the order of DAC -> ... -> pin,
23 * for input, pin -> ... -> ADC.
27 * multi[] indicates whether it's a selector widget with multi-connectors
49 bool pin_fixed:1; /* path with fixed pin */
53 /* mic/line-in auto switching entry */
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/Linux-v6.1/Documentation/driver-api/gpio/
Dintro.rst16 - The descriptor-based interface is the preferred way to manipulate GPIOs,
18 - The legacy integer-based interface which is considered deprecated (but still
21 The remainder of this document applies to the new descriptor-based interface.
23 integer-based interface.
29 A "General Purpose Input/Output" (GPIO) is a flexible software-controlled
32 represents a bit connected to a particular pin, or "ball" on Ball Grid Array
35 passes such pin configuration data to drivers.
37 System-on-Chip (SOC) processors heavily rely on GPIOs. In some cases, every
38 non-dedicated pin can be configured as a GPIO; and most chips have at least
41 often have a few such pins to help with pin scarcity on SOCs; and there are
[all …]
/Linux-v6.1/Documentation/devicetree/bindings/iio/adc/
Drenesas,rcar-gyroadc.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/iio/adc/renesas,rcar-gyroadc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas R-Car GyroADC
10 - Marek Vasut <marek.vasut+renesas@gmail.com>
15 are sampled by the GyroADC block in a round-robin fashion and the result
23 - enum:
24 - renesas,r8a7791-gyroadc
25 - renesas,r8a7792-gyroadc
[all …]
/Linux-v6.1/drivers/staging/iio/Documentation/
Dsysfs-bus-iio-dds4 Contact: linux-iio@vger.kernel.org
8 which allows for pin controlled FSK Frequency Shift Keying
15 Contact: linux-iio@vger.kernel.org
18 obtain the desired value in Hz. If shared across all frequency
20 if shared across all channels.
24 Contact: linux-iio@vger.kernel.org
34 Contact: linux-iio@vger.kernel.org
38 allows for pin controlled PSK Phase Shift Keying
45 Contact: linux-iio@vger.kernel.org
48 the desired value in rad. If shared across all phase registers
[all …]
/Linux-v6.1/drivers/gpu/drm/amd/amdgpu/
Damdgpu_dma_buf.c40 #include <linux/dma-buf.h>
41 #include <linux/dma-fence-array.h>
42 #include <linux/pci-p2pdma.h>
46 * amdgpu_dma_buf_attach - &dma_buf_ops.attach implementation
48 * @dmabuf: DMA-buf where we attach to
51 * Add the attachment as user to the exported DMA-buf.
56 struct drm_gem_object *obj = dmabuf->priv; in amdgpu_dma_buf_attach()
58 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); in amdgpu_dma_buf_attach()
61 if (pci_p2pdma_distance(adev->pdev, attach->dev, false) < 0) in amdgpu_dma_buf_attach()
62 attach->peer2peer = false; in amdgpu_dma_buf_attach()
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/Linux-v6.1/arch/arm64/boot/dts/mediatek/
Dmt7622-rfb1.dts6 * SPDX-License-Identifier: (GPL-2.0 OR MIT)
9 /dts-v1/;
10 #include <dt-bindings/input/input.h>
11 #include <dt-bindings/gpio/gpio.h>
18 compatible = "mediatek,mt7622-rfb1", "mediatek,mt7622";
25 stdout-path = "serial0:115200n8";
31 proc-supply = <&mt6380_vcpu_reg>;
32 sram-supply = <&mt6380_vm_reg>;
36 proc-supply = <&mt6380_vcpu_reg>;
37 sram-supply = <&mt6380_vm_reg>;
[all …]
Dmt7622-bananapi-bpi-r64.dts5 * SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 /dts-v1/;
9 #include <dt-bindings/input/input.h>
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/leds/common.h>
17 model = "Bananapi BPI-R64";
18 compatible = "bananapi,bpi-r64", "mediatek,mt7622";
25 stdout-path = "serial0:115200n8";
31 proc-supply = <&mt6380_vcpu_reg>;
32 sram-supply = <&mt6380_vm_reg>;
[all …]
/Linux-v6.1/drivers/net/ethernet/intel/ixgb/
Dixgb_ee.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2008 Intel Corporation. */
23 * hw - Struct containing variables accessed by shared code
24 * eecd_reg - EECD's current value
42 * hw - Struct containing variables accessed by shared code
43 * eecd_reg - EECD's current value
61 * hw - Struct containing variables accessed by shared code
62 * data - data to send to the EEPROM
63 * count - number of bits to shift out
77 mask = 0x01 << (count - 1); in ixgb_shift_out_bits()
[all …]
/Linux-v6.1/Documentation/devicetree/bindings/gpio/
Dibm,ppc4xx-gpio.txt3 All GPIOs are pin-shared with other functions. DCRs control whether a
4 particular pin that has GPIO capabilities acts as a GPIO or is used for
6 an open-drain driver.
9 - compatible: must be "ibm,ppc4xx-gpio"
10 - reg: address and length of the register set for the device
11 - #gpio-cells: must be set to 2. The first cell is the pin number
15 - gpio-controller: marks the device node as a gpio controller.
20 compatible = "ibm,ppc4xx-gpio";
22 #gpio-cells = <2>;
23 gpio-controller;
Dbrcm,brcmstb-gpio.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/brcm,brcmstb-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 The controller's registers are organized as sets of eight 32-bit
12 interrupt is shared for all of the banks handled by the controller.
15 - Doug Berger <opendmb@gmail.com>
16 - Florian Fainelli <f.fainelli@gmail.com>
21 - enum:
22 - brcm,bcm7445-gpio
[all …]
Dgpio_atmel.txt4 - compatible: "atmel,<chip>-gpio", where <chip> is at91rm9200 or at91sam9x5.
5 - reg: Should contain GPIO controller registers location and length
6 - interrupts: Should be the port interrupt shared by all the pins.
7 - #gpio-cells: Should be two. The first cell is the pin number and
10 - gpio-controller: Marks the device node as a GPIO controller.
11 - interrupt-controller: Marks the device node as an interrupt controller.
12 - #interrupt-cells: Should be two. The first cell is the pin number and the
14 in interrupt-controller/interrupts.txt for details.
17 - #gpio-lines: Number of gpio if absent 32.
22 compatible = "atmel,at91rm9200-gpio";
[all …]
/Linux-v6.1/arch/arm/mach-orion5x/
Dboard-mss2.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Maxtor Shared Storage II Board Setup
13 #include <asm/mach-types.h>
17 #include "bridge-regs.h"
21 * Maxtor Shared Storage II Info
27 static int __init mss2_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) in mss2_pci_map_irq() argument
32 * Check for devices with hard-wired IRQs. in mss2_pci_map_irq()
34 irq = orion5x_pci_map_irq(dev, slot, pin); in mss2_pci_map_irq()
35 if (irq != -1) in mss2_pci_map_irq()
38 return -1; in mss2_pci_map_irq()
[all …]
/Linux-v6.1/Documentation/devicetree/bindings/input/
Dnvidia,tegra20-kbc.txt2 The key controller has maximum 24 pins to make matrix keypad. Any pin
3 can be configured as row or column. The maximum column pin can be 8
7 - compatible: "nvidia,tegra20-kbc"
8 - reg: Register base address of KBC.
9 - interrupts: Interrupt number for the KBC.
10 - nvidia,kbc-row-pins: The KBC pins which are configured as row. This is an
11 array of pin numbers which is used as rows.
12 - nvidia,kbc-col-pins: The KBC pins which are configured as column. This is an
13 array of pin numbers which is used as column.
14 - linux,keymap: The keymap for keys as described in the binding document
[all …]
/Linux-v6.1/Documentation/devicetree/bindings/pinctrl/
Dfsl,imx-pinctrl.txt10 Please refer to pinctrl-bindings.txt in this directory for details of the
12 phrase "pin configuration node".
14 Freescale IMX pin configuration node is a node of a group of pins which can be
17 mode) this pin can work on and the 'config' configures various pad settings
18 such as pull-up, open drain, drive strength, etc.
21 - compatible: "fsl,<soc>-iomuxc"
22 Please refer to each fsl,<soc>-pinctrl.txt binding doc for supported SoCs.
24 Required properties for pin configuration node:
25 - fsl,pins: each entry consists of 6 integers and represents the mux and config
26 setting for one pin. The first 5 integers <mux_reg conf_reg input_reg mux_val
[all …]
Dintel,pinctrl-keembay.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/intel,pinctrl-keembay.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Intel Keem Bay pin controller
10 - Lakshmi Sowjanya D <lakshmi.sowjanya.d@intel.com>
13 Intel Keem Bay SoC integrates a pin controller which enables control
14 of pin directions, input/output values and configuration
19 const: intel,keembay-pinctrl
24 gpio-controller: true
[all …]
Datmel,at91-pinctrl.txt10 Please refer to pinctrl-bindings.txt in this directory for details of the
12 phrase "pin configuration node".
14 Atmel AT91 pin configuration node is a node of a group of pins which can be
16 of the pins in that group. The 'pins' selects the function mode(also named pin
17 mode) this pin can work on and the 'config' configures various pad settings
18 such as pull-up, multi drive, etc.
21 - compatible: "atmel,at91rm9200-pinctrl" or "atmel,at91sam9x5-pinctrl"
22 or "atmel,sama5d3-pinctrl" or "microchip,sam9x60-pinctrl"
23 - atmel,mux-mask: array of mask (periph per bank) to describe if a pin can be
41 For each peripheral/bank we will describe in a u32 if a pin can be
[all …]
/Linux-v6.1/arch/arm/boot/dts/
Dste-href-tvk1281618-r2.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
6 #include <dt-bindings/interrupt-controller/irq.h>
7 #include <dt-bindings/input/input.h>
11 compatible = "gpio-keys";
12 #address-cells = <1>;
13 #size-cells = <0>;
14 vdd-supply = <&ab8500_ldo_aux1_reg>;
15 pinctrl-names = "default";
16 pinctrl-0 = <&prox_tvk_mode>, <&hall_tvk_mode>;
37 interrupt-parent = <&gpio6>;
[all …]
/Linux-v6.1/arch/mips/pci/
Dfixup-ip32.c1 // SPDX-License-Identifier: GPL-2.0
27 {0, 0, 0, 0, 0}, /* This is placeholder row - never used */
37 * Given a PCI slot number (a la PCI_SLOT(...)) and the interrupt pin of
38 * the device (1-4 => A-D), tell what irq to use. Note that we don't
39 * in theory have slots 4 and 5, and we never normally use the shared
40 * irqs. I suppose a device without a pin A will thank us for doing it
43 int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) in pcibios_map_irq() argument
45 return irq_tab_mace[slot][pin]; in pcibios_map_irq()
/Linux-v6.1/arch/mips/include/asm/mach-au1x00/
Dgpio-au1000.h12 #include <asm/mach-au1x00/au1000.h>
15 * GPIO0-31 from GPIO1 block, GPIO200-215 from GPIO2 block.
22 #define ALCHEMY_GPIO1_MAX (ALCHEMY_GPIO1_BASE + ALCHEMY_GPIO1_NUM - 1)
23 #define ALCHEMY_GPIO2_MAX (ALCHEMY_GPIO2_BASE + ALCHEMY_GPIO2_NUM - 1)
47 return MAKE_IRQ(1, gpio - ALCHEMY_GPIO1_BASE); in au1000_gpio1_to_irq()
52 return -ENXIO; in au1000_gpio2_to_irq()
58 return ALCHEMY_GPIO1_BASE + (irq - AU1000_GPIO0_INT) + 0; in au1000_irq_to_gpio()
60 return -ENXIO; in au1000_irq_to_gpio()
65 gpio -= ALCHEMY_GPIO1_BASE; in au1500_gpio1_to_irq()
73 return -ENXIO; in au1500_gpio1_to_irq()
[all …]
/Linux-v6.1/Documentation/spi/
Dspi-lm70llp.rst2 spi_lm70llp : LM70-LLP parport-to-SPI adapter
15 -----------
27 --------------------
28 The schematic for this particular board (the LM70EVAL-LLP) is
39 D0 2 - -
40 D1 3 --> V+ 5
41 D2 4 --> V+ 5
42 D3 5 --> V+ 5
43 D4 6 --> V+ 5
44 D5 7 --> nCS 8
[all …]

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