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/Linux-v6.1/Documentation/devicetree/bindings/phy/
Dti,phy-am654-serdes.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/ti,phy-am654-serdes.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: TI AM654 SERDES binding
10 This binding describes the TI AM654 SERDES. AM654 SERDES can be configured
14 - Kishon Vijay Abraham I <kishon@ti.com>
19 - ti,phy-am654-serdes
24 reg-names:
26 - const: serdes
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Dqcom,qmp-usb3-dp-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: "http://devicetree.org/schemas/phy/qcom,qmp-usb3-dp-phy.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
11 - Wesley Cheng <quic_wcheng@quicinc.com>
16 - qcom,sc7180-qmp-usb3-dp-phy
17 - qcom,sc7280-qmp-usb3-dp-phy
18 - qcom,sc8180x-qmp-usb3-dp-phy
19 - qcom,sc8280xp-qmp-usb43dp-phy
20 - qcom,sdm845-qmp-usb3-dp-phy
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Dqcom,msm8996-qmp-pcie-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/qcom,msm8996-qmp-pcie-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Vinod Koul <vkoul@kernel.org>
18 const: qcom,msm8996-qmp-pcie-phy
22 - description: serdes
24 "#address-cells":
27 "#size-cells":
35 clock-names:
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Dqcom,qmp-ufs-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/qcom,qmp-ufs-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Vinod Koul <vkoul@kernel.org>
19 - qcom,msm8996-qmp-ufs-phy
20 - qcom,msm8998-qmp-ufs-phy
21 - qcom,sc8180x-qmp-ufs-phy
22 - qcom,sc8280xp-qmp-ufs-phy
23 - qcom,sdm845-qmp-ufs-phy
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/Linux-v6.1/drivers/net/ethernet/stmicro/stmmac/
Ddwmac-intel.h1 /* SPDX-License-Identifier: GPL-2.0 */
11 /* SERDES Register */
16 /* SERDES defines */
17 #define SERDES_PLL_CLK BIT(0) /* PLL clk valid signal */
18 #define SERDES_PHY_RX_CLK BIT(1) /* PSE SGMII PHY rx clk */
19 #define SERDES_RST BIT(2) /* Serdes Reset */
20 #define SERDES_PWR_ST_MASK GENMASK(6, 4) /* Serdes Power state*/
40 /* Cross-timestamping defines */
Ddwmac-intel.c1 // SPDX-License-Identifier: GPL-2.0
5 #include <linux/clk-provider.h>
8 #include "dwmac-intel.h"
14 int mdio_adhoc_addr; /* mdio address for serdes & etc */
44 int func = PCI_FUNC(pdev->devfn); in stmmac_pci_find_phy_addr()
49 return -ENODEV; in stmmac_pci_find_phy_addr()
51 dmi_data = dmi_id->driver_data; in stmmac_pci_find_phy_addr()
52 func_data = dmi_data->func; in stmmac_pci_find_phy_addr()
54 for (n = 0; n < dmi_data->nfuncs; n++, func_data++) in stmmac_pci_find_phy_addr()
55 if (func_data->func == func) in stmmac_pci_find_phy_addr()
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/Linux-v6.1/drivers/phy/xilinx/
Dphy-zynqmp.c1 // SPDX-License-Identifier: GPL-2.0
3 * phy-zynqmp.c - PHY driver for Xilinx ZynqMP GT.
5 * Copyright (C) 2018-2020 Xilinx Inc.
16 #include <linux/clk.h>
26 #include <dt-bindings/phy/phy.h>
32 /* TX De-emphasis parameters */
171 * struct xpsgtr_ssc - structure to hold SSC settings for a lane
173 * @pll_ref_clk: value to be written to register for corresponding ref clk rate
185 * struct xpsgtr_phy - representation of a lane
205 * struct xpsgtr_dev - representation of a ZynMP GT device
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/Linux-v6.1/drivers/phy/qualcomm/
Dphy-qcom-qmp-pcie-msm8996.c1 // SPDX-License-Identifier: GPL-2.0
6 #include <linux/clk.h>
7 #include <linux/clk-provider.h>
23 #include <dt-bindings/phy/phy.h>
25 #include "phy-qcom-qmp.h"
51 * if yes, then offset gives index in the reg-layout
83 /* set of registers with offsets different per-PHY */
187 /* struct qmp_phy_cfg - per-PHY initialization config */
192 /* Init sequence for PHY blocks - serdes, tx, rx, pcs */
229 * struct qmp_phy - per-lane phy descriptor
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Dphy-qcom-qmp-combo.c1 // SPDX-License-Identifier: GPL-2.0
6 #include <linux/clk.h>
7 #include <linux/clk-provider.h>
23 #include <dt-bindings/phy/phy.h>
25 #include "phy-qcom-qmp.h"
74 * if yes, then offset gives index in the reg-layout
106 /* set of registers with offsets different per-PHY */
753 { .name = "vdda-phy", .enable_load = 21800 },
754 { .name = "vdda-pll", .enable_load = 36000 },
815 /* struct qmp_phy_cfg - per-PHY initialization config */
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Dphy-qcom-qmp-ufs.c1 // SPDX-License-Identifier: GPL-2.0
6 #include <linux/clk.h>
7 #include <linux/clk-provider.h>
23 #include <dt-bindings/phy/phy.h>
25 #include "phy-qcom-qmp.h"
46 * if yes, then offset gives index in the reg-layout
78 /* set of registers with offsets different per-PHY */
534 /* struct qmp_phy_cfg - per-PHY initialization config */
538 /* Init sequence for PHY blocks - serdes, tx, rx, pcs */
568 * struct qmp_phy - per-lane phy descriptor
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Dphy-qcom-qmp-pcie.c1 // SPDX-License-Identifier: GPL-2.0
6 #include <linux/clk.h>
7 #include <linux/clk-provider.h>
23 #include <dt-bindings/phy/phy.h>
25 #include "phy-qcom-qmp.h"
46 * if yes, then offset gives index in the reg-layout
78 /* set of registers with offsets different per-PHY */
1303 /* struct qmp_phy_cfg - per-PHY initialization config */
1307 /* Init sequence for PHY blocks - serdes, tx, rx, pcs */
1358 * struct qmp_phy - per-lane phy descriptor
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Dphy-qcom-qmp-usb.c1 // SPDX-License-Identifier: GPL-2.0
6 #include <linux/clk.h>
7 #include <linux/clk-provider.h>
23 #include <dt-bindings/phy/phy.h>
25 #include "phy-qcom-qmp.h"
74 * if yes, then offset gives index in the reg-layout
106 /* set of registers with offsets different per-PHY */
1430 /* struct qmp_phy_cfg - per-PHY initialization config */
1434 /* Init sequence for PHY blocks - serdes, tx, rx, pcs */
1478 * struct qmp_phy - per-lane phy descriptor
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/Linux-v6.1/drivers/phy/ti/
Dphy-j721e-wiz.c1 // SPDX-License-Identifier: GPL-2.0
3 * Wrapper driver for SERDES used in J721E
5 * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
9 #include <dt-bindings/phy/phy.h>
10 #include <dt-bindings/phy/phy-ti.h>
12 #include <linux/clk.h>
13 #include <linux/clk-provider.h>
25 #include <linux/reset-controller.h>
35 /* SERDES offsets */
111 [TI_WIZ_PLL0_REFCLK] = "pll0-refclk",
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Dphy-am654-serdes.c1 // SPDX-License-Identifier: GPL-2.0
3 * PCIe SERDES driver for AM654x SoC
5 * Copyright (C) 2018 - 2019 Texas Instruments Incorporated - http://www.ti.com/
9 #include <dt-bindings/phy/phy.h>
10 #include <linux/clk.h>
11 #include <linux/clk-provider.h>
142 /* Mid-speed initial calibration control */
145 /* High-speed initial calibration control */
148 /* Mid-speed recalibration control */
151 /* High-speed recalibration control */
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/Linux-v6.1/drivers/phy/samsung/
Dphy-exynos5250-sata.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Samsung SATA SerDes(PHY) driver
10 #include <linux/clk.h>
50 struct clk *phyclk;
66 return -EFAULT; in wait_for_reg_status()
73 return regmap_update_bits(sata_phy->pmureg, SATAPHY_CONTROL_OFFSET, in exynos_sata_phy_power_on()
82 return regmap_update_bits(sata_phy->pmureg, SATAPHY_CONTROL_OFFSET, in exynos_sata_phy_power_off()
94 ret = regmap_update_bits(sata_phy->pmureg, SATAPHY_CONTROL_OFFSET, in exynos_sata_phy_init()
97 dev_err(&sata_phy->phy->dev, "phy init failed\n"); in exynos_sata_phy_init()
99 writel(val, sata_phy->regs + EXYNOS5_SATA_RESET); in exynos_sata_phy_init()
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/Linux-v6.1/arch/arm64/boot/dts/freescale/
Dfsl-ls1028a-kontron-sl28-var1.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * Device Tree file for the Kontron SMARC-sAL28 board.
8 * None of the four SerDes lanes are used by the module, instead they are
15 /dts-v1/;
16 #include "fsl-ls1028a-kontron-sl28.dts"
17 #include <dt-bindings/net/qca-ar803x.h>
20 model = "Kontron SMARC-sAL28 (4 Lanes)";
21 compatible = "kontron,sl28-var1", "kontron,sl28", "fsl,ls1028a";
26 /delete-node/ ethernet-phy@5;
28 phy0: ethernet-phy@4 {
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/Linux-v6.1/drivers/phy/marvell/
Dphy-mvebu-a3700-comphy.c1 // SPDX-License-Identifier: GPL-2.0
11 * Structure inspired from phy-mvebu-cp110-comphy.c written by Antoine Tenart.
17 #include <linux/clk.h>
40 * since the registers are 16-bit.
183 #define COMPHY_PHY_REG(lane, reg) (((1 - (lane)) * 0x28) + ((reg) & 0x3f))
300 /*-----------------------------------------------------------*/
391 priv->lane2_phy_indirect + COMPHY_LANE2_INDIR_ADDR); in comphy_set_indirect()
392 comphy_reg_set(priv->lane2_phy_indirect + COMPHY_LANE2_INDIR_DATA, in comphy_set_indirect()
399 if (lane->id == 2) { in comphy_lane_reg_set()
401 comphy_set_indirect(lane->priv, in comphy_lane_reg_set()
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/Linux-v6.1/arch/mips/boot/dts/mscc/
Docelot.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
5 #address-cells = <1>;
6 #size-cells = <1>;
10 #address-cells = <1>;
11 #size-cells = <0>;
25 cpuintc: interrupt-controller {
26 #address-cells = <0>;
27 #interrupt-cells = <1>;
28 interrupt-controller;
29 compatible = "mti,cpu-interrupt-controller";
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/Linux-v6.1/drivers/phy/microchip/
Dsparx5_serdes.c1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* Microchip Sparx5 Switch SerDes driver
7 * https://github.com/microchip-ung/sparx-5_reginfo
9 …* https://ww1.microchip.com/downloads/en/DeviceDoc/SparX-5_Family_L2L3_Enterprise_10G_Ethernet_Swi…
18 #include <linux/clk.h>
99 u8 if_width; /* UDL if-width: 10/16/20/32/64 */
101 enum sparx5_10g28cmu_mode cmu_sel; /* Device/Mode serdes uses */
102 bool no_pwrcycle:1; /* Omit initial power-cycle */
231 enum sparx5_10g28cmu_mode cmu_sel; /* Device/Mode serdes uses */
241 bool no_pwrcycle:1; /* Omit initial power-cycle */
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/Linux-v6.1/arch/arm64/boot/dts/microchip/
Dsparx5.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/clock/microchip,sparx5.h>
12 interrupt-parent = <&gic>;
13 #address-cells = <2>;
14 #size-cells = <1>;
23 stdout-path = "serial0:115200n8";
27 #address-cells = <2>;
28 #size-cells = <0>;
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/Linux-v6.1/drivers/net/ethernet/atheros/atl1c/
Datl1c_hw.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Copyright(c) 2008 - 2009 Atheros Corporation. All rights reserved.
6 * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
56 /* hw-ids */
152 * ->L0s not L1 */
171 #define PM_CTRL_CLK_SWH_L1 BIT(13) /* en pcie clk sw in L1 */
179 #define PM_CTRL_SERDES_PD_EX_L1 BIT(6) /* power down serdes rx */
200 * serdes, not sw to 25M */
207 #define MASTER_CTRL_WAKEN_25M BIT(5) /* WAKE WO. PCIE CLK */
293 #define MDIO_MAX_AC_TO 120 /* 1.2ms timeout for slow clk */
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/Linux-v6.1/drivers/pci/controller/
Dpcie-brcmstb.c1 // SPDX-License-Identifier: GPL-2.0+
2 /* Copyright (C) 2009 - 2019 Broadcom */
6 #include <linux/clk.h>
25 #include <linux/pci-ecam.h>
36 /* BRCM_PCIE_CAP_REGS - Offset for the mandatory capability config regs */
149 #define BRCM_INT_PCI_MSI_MASK GENMASK(BRCM_INT_PCI_MSI_NR - 1, 0)
151 32 - BRCM_INT_PCI_MSI_LEGACY_NR)
178 #define IDX_ADDR(pcie) (pcie->reg_offsets[EXT_CFG_INDEX])
179 #define DATA_ADDR(pcie) (pcie->reg_offsets[EXT_CFG_DATA])
180 #define PCIE_RGR1_SW_INIT_1(pcie) (pcie->reg_offsets[RGR1_SW_INIT_1])
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/Linux-v6.1/arch/arm64/boot/dts/ti/
Dk3-am65-main.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2016-2018 Texas Instruments Incorporated - https://www.ti.com/
7 #include <dt-bindings/phy/phy-am654-serdes.h>
11 compatible = "mmio-sram";
13 #address-cells = <1>;
14 #size-cells = <1>;
17 atf-sram@0 {
21 sysfw-sram@f0000 {
25 l3cache-sram@100000 {
30 gic500: interrupt-controller@1800000 {
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/Linux-v6.1/sound/soc/apple/
Dmca.c1 // SPDX-License-Identifier: GPL-2.0-only
9 // four SERDES units and has a dedicated I2S port on the SoC's periphery.
12 // configurable manner. We mostly treat them as self-contained independent
13 // units and don't configure any cross-cluster connections except for the I2S
24 #include <linux/clk.h>
25 #include <linux/dma-mapping.h>
71 /* Bases of serdes units (relative to cluster) */
85 /* Relative to serdes unit base */
134 struct clk *clk_parent;
170 __iomem void *ptr = cl->base + regoffset; in mca_modify()
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/Linux-v6.1/drivers/phy/
Dphy-xgene.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * AppliedMicro X-Gene Multi-purpose PHY driver
10 * The APM X-Gene PHY consists of two PLL clock macro's (CMU) and lanes.
19 * -----------------
20 * | Internal | |------|
21 * | Ref PLL CMU |----| | ------------- ---------
22 * ------------ ---- | MUX |-----|PHY PLL CMU|----| Serdes|
23 * | | | | ---------
24 * External Clock ------| | -------------
25 * |------|
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