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Searched +full:sdm845 +full:- +full:dispcc (Results 1 – 14 of 14) sorted by relevance

/Linux-v5.15/Documentation/devicetree/bindings/display/msm/
Ddpu-sdm845.yaml1 # SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/dpu-sdm845.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Display DPU dt properties for SDM845 target
10 - Krishna Manikandan <mkrishn@codeaurora.org>
14 sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
15 bindings of MDSS and DPU are mentioned for SDM845 target.
20 - const: qcom,sdm845-mdss
25 reg-names:
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Ddsi-controller-main.yaml1 # SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/dsi-controller-main.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krishna Manikandan <mkrishn@codeaurora.org>
13 - $ref: "../dsi-controller.yaml#"
18 - const: qcom,mdss-dsi-ctrl
23 reg-names:
31 - description: Display byte clock
32 - description: Display byte interface clock
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Ddsi-phy-10nm.yaml1 # SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/dsi-phy-10nm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krishna Manikandan <mkrishn@codeaurora.org>
13 - $ref: dsi-phy-common.yaml#
18 - qcom,dsi-phy-10nm
19 - qcom,dsi-phy-10nm-8998
23 - description: dsi phy register set
24 - description: dsi phy lane register set
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Ddpu-sc7180.yaml1 # SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/dpu-sc7180.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krishna Manikandan <mkrishn@codeaurora.org>
14 sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
20 - const: qcom,sc7180-mdss
25 reg-names:
28 power-domains:
33 - description: Display AHB clock from gcc
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Ddsi-phy-14nm.yaml1 # SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/dsi-phy-14nm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krishna Manikandan <mkrishn@codeaurora.org>
13 - $ref: dsi-phy-common.yaml#
18 - qcom,dsi-phy-14nm
19 - qcom,dsi-phy-14nm-660
23 - description: dsi phy register set
24 - description: dsi phy lane register set
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Ddsi-phy-28nm.yaml1 # SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/dsi-phy-28nm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krishna Manikandan <mkrishn@codeaurora.org>
13 - $ref: dsi-phy-common.yaml#
18 - qcom,dsi-phy-28nm-hpm
19 - qcom,dsi-phy-28nm-lp
20 - qcom,dsi-phy-28nm-8960
24 - description: dsi pll register set
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Ddsi-phy-20nm.yaml1 # SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/dsi-phy-20nm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krishna Manikandan <mkrishn@codeaurora.org>
13 - $ref: dsi-phy-common.yaml#
17 const: qcom,dsi-phy-20nm
21 - description: dsi pll register set
22 - description: dsi phy register set
23 - description: dsi phy regulator register set
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/Linux-v5.15/Documentation/devicetree/bindings/clock/
Dqcom,sdm845-dispcc.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,sdm845-dispcc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Display Clock & Reset Controller Binding for SDM845
10 - Taniya Das <tdas@codeaurora.org>
14 power domains on SDM845.
16 See also dt-bindings/clock/qcom,dispcc-sdm845.h.
20 const: qcom,sdm845-dispcc
22 # NOTE: sdm845.dtsi existed for quite some time and specified no clocks.
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/Linux-v5.15/drivers/clk/qcom/
DMakefile1 # SPDX-License-Identifier: GPL-2.0
2 obj-$(CONFIG_COMMON_CLK_QCOM) += clk-qcom.o
4 clk-qcom-y += common.o
5 clk-qcom-y += clk-regmap.o
6 clk-qcom-y += clk-alpha-pll.o
7 clk-qcom-y += clk-pll.o
8 clk-qcom-y += clk-rcg.o
9 clk-qcom-y += clk-rcg2.o
10 clk-qcom-y += clk-branch.o
11 clk-qcom-y += clk-regmap-divider.o
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Ddispcc-sdm845.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
6 #include <linux/clk-provider.h>
10 #include <linux/reset-controller.h>
12 #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
14 #include "clk-alpha-pll.h"
15 #include "clk-branch.h"
16 #include "clk-rcg.h"
17 #include "clk-regmap-divider.h"
842 { .compatible = "qcom,sdm845-dispcc" },
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/Linux-v5.15/arch/arm64/boot/dts/qcom/
Dsdm845.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * SDM845 SoC device tree source
8 #include <dt-bindings/clock/qcom,camcc-sdm845.h>
9 #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
10 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
11 #include <dt-bindings/clock/qcom,gpucc-sdm845.h>
12 #include <dt-bindings/clock/qcom,lpass-sdm845.h>
13 #include <dt-bindings/clock/qcom,rpmh.h>
14 #include <dt-bindings/clock/qcom,videocc-sdm845.h>
15 #include <dt-bindings/interconnect/qcom,osm-l3.h>
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Dsc7180.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
5 * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
8 #include <dt-bindings/clock/qcom,dispcc-sc7180.h>
9 #include <dt-bindings/clock/qcom,gcc-sc7180.h>
10 #include <dt-bindings/clock/qcom,gpucc-sc7180.h>
11 #include <dt-bindings/clock/qcom,lpasscorecc-sc7180.h>
12 #include <dt-bindings/clock/qcom,rpmh.h>
13 #include <dt-bindings/clock/qcom,videocc-sc7180.h>
14 #include <dt-bindings/interconnect/qcom,osm-l3.h>
15 #include <dt-bindings/interconnect/qcom,sc7180.h>
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Dsc7280.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
5 * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
8 #include <dt-bindings/clock/qcom,gcc-sc7280.h>
9 #include <dt-bindings/clock/qcom,rpmh.h>
10 #include <dt-bindings/interconnect/qcom,sc7280.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/mailbox/qcom-ipcc.h>
13 #include <dt-bindings/power/qcom-aoss-qmp.h>
14 #include <dt-bindings/power/qcom-rpmpd.h>
15 #include <dt-bindings/reset/qcom,sdm845-aoss.h>
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/Linux-v5.15/drivers/phy/qualcomm/
Dphy-qcom-qmp.c1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/clk-provider.h>
23 #include <dt-bindings/phy/phy.h>
25 #include "phy-qcom-qmp.h"
84 * if yes, then offset gives index in the reg-layout
116 /* set of registers with offsets different per-PHY */
2766 /* struct qmp_phy_cfg - per-PHY initialization config */
2768 /* phy-type - PCIE/UFS/USB */
2773 /* Init sequence for PHY blocks - serdes, tx, rx, pcs */
2855 * struct qmp_phy - per-lane phy descriptor
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