Searched +full:sd1 +full:- +full:pwr +full:- +full:en +full:- +full:hog (Results 1 – 5 of 5) sorted by relevance
1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)8 #include <dt-bindings/gpio/gpio.h>9 #include <dt-bindings/pinctrl/rzg2l-pinctrl.h>12 pinctrl-0 = <&sound_clk_pins>;13 pinctrl-names = "default";21 can0-stb-hog {22 gpio-hog;24 output-low;25 line-name = "can0_stb";35 can1-stb-hog {[all …]
1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)8 #include <dt-bindings/gpio/gpio.h>9 #include <dt-bindings/pinctrl/rzg2l-pinctrl.h>12 pinctrl-0 = <&sound_clk_pins>;13 pinctrl-names = "default";20 /* SW7 should be at position 2->3 so that GPIO8_CAN0_STB line is activated */21 can0-stb-hog {22 gpio-hog;24 output-low;25 line-name = "can0_stb";[all …]
1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)8 #include <dt-bindings/gpio/gpio.h>9 #include <dt-bindings/pinctrl/rzg2l-pinctrl.h>12 pinctrl-0 = <&sound_clk_pins>;13 pinctrl-names = "default";16 /* SW8 should be at position 2->1 */24 /* SW8 should be at position 2->3 so that GPIO9_CAN1_STB line is activated */25 can1-stb-hog {26 gpio-hog;28 output-low;[all …]
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)3 ---4 $id: http://devicetree.org/schemas/pinctrl/renesas,rzg2l-pinctrl.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#10 - Geert Uytterhoeven <geert+renesas@glider.be>11 - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>16 Pin multiplexing and GPIO configuration is performed on a per-pin basis.24 - items:25 - enum:26 - renesas,r9a07g043-pinctrl # RZ/G2UL{Type-1,Type-2} and RZ/Five[all …]
1 // SPDX-License-Identifier: GPL-2.03 #include <dt-bindings/input/input.h>4 #include <dt-bindings/input/gpio-keys.h>5 #include <dt-bindings/mfd/max77620.h>6 #include <dt-bindings/pinctrl/pinctrl-tegra.h>16 stdout-path = "serial0:115200n8";26 pinctrl-names = "boot";27 pinctrl-0 = <&state_boot>;35 nvidia,enable-input = <TEGRA_PIN_DISABLE>;36 nvidia,open-drain = <TEGRA_PIN_DISABLE>;[all …]
