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/Linux-v5.15/Documentation/devicetree/bindings/display/msm/
Ddpu-sc7180.yaml1 # SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/dpu-sc7180.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Display DPU dt properties for SC7180 target
10 - Krishna Manikandan <mkrishn@codeaurora.org>
13 Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates
14 sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
15 bindings of MDSS and DPU are mentioned for SC7180 target.
20 - const: qcom,sc7180-mdss
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Ddp-controller.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/msm/dp-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Kuogee Hsieh <khsieh@codeaurora.org>
19 - qcom,sc7180-dp
29 - description: AHB clock to enable register access
30 - description: Display Port AUX clock
31 - description: Display Port Link clock
32 - description: Link interface clock between DP and PHY
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/Linux-v5.15/drivers/iommu/arm/arm-smmu/
Darm-smmu-qcom.c1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/adreno-smmu-priv.h>
11 #include "arm-smmu.h"
36 if (qsmmu->stall_enabled & BIT(idx)) in qcom_adreno_smmu_write_sctlr()
46 struct arm_smmu_cfg *cfg = &smmu_domain->cfg; in qcom_adreno_smmu_get_fault_info()
47 struct arm_smmu_device *smmu = smmu_domain->smmu; in qcom_adreno_smmu_get_fault_info()
49 info->fsr = arm_smmu_cb_read(smmu, cfg->cbndx, ARM_SMMU_CB_FSR); in qcom_adreno_smmu_get_fault_info()
50 info->fsynr0 = arm_smmu_cb_read(smmu, cfg->cbndx, ARM_SMMU_CB_FSYNR0); in qcom_adreno_smmu_get_fault_info()
51 info->fsynr1 = arm_smmu_cb_read(smmu, cfg->cbndx, ARM_SMMU_CB_FSYNR1); in qcom_adreno_smmu_get_fault_info()
52 info->far = arm_smmu_cb_readq(smmu, cfg->cbndx, ARM_SMMU_CB_FAR); in qcom_adreno_smmu_get_fault_info()
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/Linux-v5.15/arch/arm64/boot/dts/qcom/
Dsc7180.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
3 * SC7180 SoC device tree source
5 * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
8 #include <dt-bindings/clock/qcom,dispcc-sc7180.h>
9 #include <dt-bindings/clock/qcom,gcc-sc7180.h>
10 #include <dt-bindings/clock/qcom,gpucc-sc7180.h>
11 #include <dt-bindings/clock/qcom,lpasscorecc-sc7180.h>
12 #include <dt-bindings/clock/qcom,rpmh.h>
13 #include <dt-bindings/clock/qcom,videocc-sc7180.h>
14 #include <dt-bindings/interconnect/qcom,osm-l3.h>
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Dsc7180-idp.dts1 // SPDX-License-Identifier: BSD-3-Clause
3 * SC7180 IDP board device tree source
8 /dts-v1/;
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
12 #include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
13 #include "sc7180.dtsi"
18 model = "Qualcomm Technologies, Inc. SC7180 IDP";
19 compatible = "qcom,sc7180-idp", "qcom,sc7180";
29 stdout-path = "serial0:115200n8";
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Dsc7180-trogdor.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/gpio-keys.h>
10 #include <dt-bindings/input/input.h>
11 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
12 #include <dt-bindings/sound/sc7180-lpass.h>
19 thermal-zones {
20 charger_thermal: charger-thermal {
21 polling-delay-passive = <0>;
22 polling-delay = <0>;
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/Linux-v5.15/drivers/gpu/drm/msm/
Dmsm_drv.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2016-2018, 2020-2021 The Linux Foundation. All rights reserved.
8 #include <linux/dma-mapping.h>
32 * - 1.0.0 - initial interface
33 * - 1.1.0 - adds madvise, and support for submits with > 4 cmd buffers
34 * - 1.2.0 - adds explicit fence support for submit ioctl
35 * - 1.3.0 - adds GMEM_BASE + NR_RINGS params, SUBMITQUEUE_NEW +
38 * - 1.4.0 - softpin, MSM_RELOC_BO_DUMP, and GEM_INFO support to set/get
40 * - 1.5.0 - Add SUBMITQUERY_QUERY ioctl
41 * - 1.6.0 - Syncobj support
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/Linux-v5.15/drivers/gpu/drm/msm/disp/dpu1/
Ddpu_hw_catalog.h1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /* Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved.
43 #define DPU_HW_VER_620 DPU_HW_VER(6, 2, 0) /* sc7180 v1.0 */
77 * @DPU_MDP_BWC, MDSS HW supports Bandwidth compression.
94 * SSPP sub-blocks/features
102 * @DPU_SSPP_CSC_10BIT, Support of 10-bit Color space conversion
105 * @DPU_SSPP_QOS_8LVL, SSPP support 8-level QoS control
136 * MIXER sub-blocks/features
138 * @DPU_MIXER_SOURCESPLIT Layer mixer supports source-split configuration
152 * DSPP sub-blocks
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