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Searched +full:sc7180 +full:- +full:dispcc (Results 1 – 8 of 8) sorted by relevance

/Linux-v6.1/Documentation/devicetree/bindings/display/msm/
Ddpu-sc7180.yaml1 # SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/dpu-sc7180.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Display DPU dt properties for SC7180 target
10 - Krishna Manikandan <quic_mkrishn@quicinc.com>
14 sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
15 bindings of MDSS and DPU are mentioned for SC7180 target.
20 - const: qcom,sc7180-mdss
25 reg-names:
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Ddp-controller.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/msm/dp-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Kuogee Hsieh <quic_khsieh@quicinc.com>
19 - qcom,sc7180-dp
20 - qcom,sc7280-dp
21 - qcom,sc7280-edp
22 - qcom,sc8180x-dp
23 - qcom,sc8180x-edp
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Ddsi-phy-10nm.yaml1 # SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/dsi-phy-10nm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krishna Manikandan <quic_mkrishn@quicinc.com>
13 - $ref: dsi-phy-common.yaml#
18 - qcom,dsi-phy-10nm
19 - qcom,dsi-phy-10nm-8998
23 - description: dsi phy register set
24 - description: dsi phy lane register set
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/Linux-v6.1/Documentation/devicetree/bindings/clock/
Dqcom,sc7180-dispcc.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,sc7180-dispcc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Display Clock & Reset Controller Binding for SC7180
10 - Taniya Das <tdas@codeaurora.org>
14 power domains on SC7180.
16 See also dt-bindings/clock/qcom,dispcc-sc7180.h.
20 const: qcom,sc7180-dispcc
24 - description: Board XO source
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/Linux-v6.1/drivers/clk/qcom/
DMakefile1 # SPDX-License-Identifier: GPL-2.0
2 obj-$(CONFIG_COMMON_CLK_QCOM) += clk-qcom.o
4 clk-qcom-y += common.o
5 clk-qcom-y += clk-regmap.o
6 clk-qcom-y += clk-alpha-pll.o
7 clk-qcom-y += clk-pll.o
8 clk-qcom-y += clk-rcg.o
9 clk-qcom-y += clk-rcg2.o
10 clk-qcom-y += clk-branch.o
11 clk-qcom-y += clk-regmap-divider.o
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Ddispcc-sc7180.c1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/clk-provider.h>
11 #include <dt-bindings/clock/qcom,dispcc-sc7180.h>
13 #include "clk-alpha-pll.h"
14 #include "clk-branch.h"
15 #include "clk-rcg.h"
16 #include "clk-regmap-divider.h"
694 { .compatible = "qcom,sc7180-dispcc" },
722 .name = "sc7180-dispcc",
739 MODULE_DESCRIPTION("QTI DISP_CC SC7180 Driver");
/Linux-v6.1/arch/arm64/boot/dts/qcom/
Dsc7180.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
3 * SC7180 SoC device tree source
5 * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
8 #include <dt-bindings/clock/qcom,dispcc-sc7180.h>
9 #include <dt-bindings/clock/qcom,gcc-sc7180.h>
10 #include <dt-bindings/clock/qcom,gpucc-sc7180.h>
11 #include <dt-bindings/clock/qcom,lpasscorecc-sc7180.h>
12 #include <dt-bindings/clock/qcom,rpmh.h>
13 #include <dt-bindings/clock/qcom,videocc-sc7180.h>
14 #include <dt-bindings/interconnect/qcom,osm-l3.h>
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/Linux-v6.1/drivers/phy/qualcomm/
Dphy-qcom-qmp-combo.c1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/clk-provider.h>
23 #include <dt-bindings/phy/phy.h>
25 #include "phy-qcom-qmp.h"
74 * if yes, then offset gives index in the reg-layout
106 /* set of registers with offsets different per-PHY */
753 { .name = "vdda-phy", .enable_load = 21800 },
754 { .name = "vdda-pll", .enable_load = 36000 },
815 /* struct qmp_phy_cfg - per-PHY initialization config */
817 /* phy-type - PCIE/UFS/USB */
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