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/Linux-v6.6/Documentation/devicetree/bindings/ata/
Dbrcm,sata-brcm.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/ata/brcm,sata-brcm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Broadcom SATA3 AHCI Controller
10 SATA nodes are defined to describe on-chip Serial ATA controllers.
14 - Florian Fainelli <f.fainelli@gmail.com>
17 - $ref: ahci-common.yaml#
22 - items:
23 - enum:
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Dapm-xgene.txt1 * APM X-Gene 6.0 Gb/s SATA host controller nodes
3 SATA host controller nodes are defined to describe on-chip Serial ATA
7 - compatible : Shall contain:
8 * "apm,xgene-ahci"
9 - reg : First memory resource shall be the AHCI memory
19 - interrupts : Interrupt-specifier for SATA host controller IRQ.
20 - clocks : Reference to the clock entry.
21 - phys : A list of phandles + phy-specifiers, one for each
22 entry in phy-names.
23 - phy-names : Should contain:
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/Linux-v6.6/drivers/ata/
Dahci_brcm.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Broadcom SATA3 AHCI Controller Driver
5 * Copyright © 2009-2015 Broadcom Corporation
22 #include "ahci.h"
24 #define DRV_NAME "brcm-ahci"
28 #define MMIO_ENDIAN_SHIFT 0 /* CPU->AHCI */
29 #define DMADESC_ENDIAN_SHIFT 2 /* AHCI->DDR */
30 #define DMADATA_ENDIAN_SHIFT 4 /* AHCI->DDR */
51 /* On big-endian MIPS, buses are reversed to big endian, so switch them back */
53 #define DATA_ENDIAN 2 /* AHCI->DDR inbound accesses */
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DKconfig1 # SPDX-License-Identifier: GPL-2.0
10 uses pata-platform driver to enable the relevant driver in the
21 If you want to use an ATA hard disk, ATA tape drive, ATA CD-ROM or
62 <file:Documentation/admin-guide/kernel-parameters.txt>.
76 This option adds support for ATA-related ACPI objects.
107 comment "Controllers with non-SFF native interface"
110 tristate "AHCI SATA support"
114 This option enables support for AHCI Serial ATA.
125 for chipsets / "South Bridges" supporting low-power modes. Such
140 tristate "Platform AHCI SATA support"
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/Linux-v6.6/arch/arm/boot/dts/marvell/
Darmada-370-seagate-nas-4bay.dts1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree file for Seagate NAS 4-Bay (Armada 370 SoC).
13 * Product name : Seagate NAS 4-Bay
14 * Code name (board/PCB) : Dart 4-Bay
19 /dts-v1/;
20 #include "armada-370-seagate-nas-xbay.dtsi"
21 #include <dt-bindings/leds/leds-ns2.h>
24 model = "Seagate NAS 4-Bay (Dart, SRPD40)";
25 compatible = "seagate,dart-4", "marvell,armada370", "marvell,armada-370-xp";
28 internal-regs {
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Darmada-38x.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 * Gregory CLEMENT <gregory.clement@free-electrons.com>
9 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/interrupt-controller/irq.h>
18 #address-cells = <1>;
19 #size-cells = <1>;
32 compatible = "arm,cortex-a9-pmu";
33 interrupts-extended = <&mpic 3>;
37 compatible = "marvell,armada380-mbus", "simple-bus";
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/Linux-v6.6/arch/arm/boot/dts/broadcom/
Dbcm63138.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/interrupt-controller/irq.h>
10 #address-cells = <1>;
11 #size-cells = <1>;
14 interrupt-parent = <&gic>;
22 #address-cells = <1>;
23 #size-cells = <0>;
27 compatible = "arm,cortex-a9";
28 next-level-cache = <&L2>;
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Dbcm7445.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #address-cells = <2>;
6 #size-cells = <2>;
9 interrupt-parent = <&gic>;
16 #address-cells = <1>;
17 #size-cells = <0>;
20 compatible = "brcm,brahma-b15";
22 enable-method = "brcm,brahma-b15";
27 compatible = "brcm,brahma-b15";
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/Linux-v6.6/arch/mips/boot/dts/brcm/
Dbcm7360.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #address-cells = <1>;
4 #size-cells = <1>;
8 #address-cells = <1>;
9 #size-cells = <0>;
11 mips-hpt-frequency = <375000000>;
24 cpu_intc: interrupt-controller {
25 #address-cells = <0>;
26 compatible = "mti,cpu-interrupt-controller";
28 interrupt-controller;
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Dbcm7362.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #address-cells = <1>;
4 #size-cells = <1>;
8 #address-cells = <1>;
9 #size-cells = <0>;
11 mips-hpt-frequency = <375000000>;
30 cpu_intc: interrupt-controller {
31 #address-cells = <0>;
32 compatible = "mti,cpu-interrupt-controller";
34 interrupt-controller;
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Dbcm7346.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #address-cells = <1>;
4 #size-cells = <1>;
8 #address-cells = <1>;
9 #size-cells = <0>;
11 mips-hpt-frequency = <163125000>;
30 cpu_intc: interrupt-controller {
31 #address-cells = <0>;
32 compatible = "mti,cpu-interrupt-controller";
34 interrupt-controller;
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Dbcm7435.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #address-cells = <1>;
4 #size-cells = <1>;
8 #address-cells = <1>;
9 #size-cells = <0>;
11 mips-hpt-frequency = <175625000>;
42 cpu_intc: interrupt-controller {
43 #address-cells = <0>;
44 compatible = "mti,cpu-interrupt-controller";
46 interrupt-controller;
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Dbcm7425.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #address-cells = <1>;
4 #size-cells = <1>;
8 #address-cells = <1>;
9 #size-cells = <0>;
11 mips-hpt-frequency = <163125000>;
30 cpu_intc: interrupt-controller {
31 #address-cells = <0>;
32 compatible = "mti,cpu-interrupt-controller";
34 interrupt-controller;
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/Linux-v6.6/arch/arm64/boot/dts/apm/
Dapm-shadowcat.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * dts file for AppliedMicro (APM) X-Gene Shadowcat SOC
9 compatible = "apm,xgene-shadowcat";
10 interrupt-parent = <&gic>;
11 #address-cells = <2>;
12 #size-cells = <2>;
15 #address-cells = <2>;
16 #size-cells = <0>;
22 enable-method = "spin-table";
23 cpu-release-addr = <0x1 0x0000fff8>;
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Dapm-storm.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * dts file for AppliedMicro (APM) X-Gene Storm SOC
9 compatible = "apm,xgene-storm";
10 interrupt-parent = <&gic>;
11 #address-cells = <2>;
12 #size-cells = <2>;
15 #address-cells = <2>;
16 #size-cells = <0>;
22 enable-method = "spin-table";
23 cpu-release-addr = <0x1 0x0000fff8>;
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/Linux-v6.6/arch/arm64/boot/dts/freescale/
Dfsl-lx2160a.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 // Device Tree Include file for Layerscape-LX2160A family SoC.
5 // Copyright 2018-2020 NXP
7 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/thermal/thermal.h>
16 interrupt-parent = <&gic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
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/Linux-v6.6/drivers/phy/broadcom/
Dphy-brcm-sata.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Broadcom SATA3 AHCI Controller PHY Driver
196 struct brcm_sata_phy *priv = port->phy_priv; in brcm_sata_ctrl_base()
199 switch (priv->version) { in brcm_sata_ctrl_base()
204 dev_err(priv->dev, "invalid phy version\n"); in brcm_sata_ctrl_base()
208 return priv->ctrl_base + (port->portnum * size); in brcm_sata_ctrl_base()
214 struct brcm_sata_phy *priv = port->phy_priv; in brcm_sata_phy_wr()
215 void __iomem *pcb_base = priv->phy_base; in brcm_sata_phy_wr()
218 if (priv->version == BRCM_SATA_PHY_STB_40NM) in brcm_sata_phy_wr()
219 bank += (port->portnum * SATA_PCB_REG_40NM_SPACE_SIZE); in brcm_sata_phy_wr()
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