| /Linux-v6.1/Documentation/devicetree/bindings/phy/ |
| D | brcm,sata-phy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: "http://devicetree.org/schemas/phy/brcm,sata-phy.yaml#"
5 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
7 title: Broadcom SATA3 PHY
10 - Florian Fainelli <f.fainelli@gmail.com>
14 pattern: "^sata[-|_]phy(@.*)?$"
18 - items:
19 - enum:
20 - brcm,bcm7216-sata-phy
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| D | qcom-apq8064-sata-phy.txt | 1 Qualcomm APQ8064 SATA PHY Controller
2 ------------------------------------
4 SATA PHY nodes are defined to describe on-chip SATA Physical layer controllers.
5 Each SATA PHY controller should have its own node.
8 - compatible: compatible list, contains "qcom,apq8064-sata-phy".
9 - reg: offset and length of the SATA PHY register set;
10 - #phy-cells: must be zero
11 - clocks: a list of phandles and clock-specifier pairs, one for each entry in
12 clock-names.
13 - clock-names: must be "cfg" for phy config clock.
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| D | qcom-ipq806x-sata-phy.txt | 1 Qualcomm IPQ806x SATA PHY Controller
2 ------------------------------------
4 SATA PHY nodes are defined to describe on-chip SATA Physical layer controllers.
5 Each SATA PHY controller should have its own node.
8 - compatible: compatible list, contains "qcom,ipq806x-sata-phy"
9 - reg: offset and length of the SATA PHY register set;
10 - #phy-cells: must be zero
11 - clocks: must be exactly one entry
12 - clock-names: must be "cfg"
15 sata_phy: sata-phy@1b400000 {
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| D | phy-miphy365x.txt | 1 STMicroelectronics STi MIPHY365x PHY binding
4 This binding describes a miphy device that is used to control PHY hardware
5 for SATA and PCIe.
8 - compatible : Should be "st,miphy365x-phy"
9 - st,syscfg : Phandle / integer array property. Phandle of sysconfig group
11 an entry for each port sub-node, specifying the control
14 Required nodes : A sub-node is required for each channel the controller
16 'reg' and 'reg-names' properties are used inside these
21 - #phy-cells : Should be 1 (See second example)
23 - PHY_TYPE_SATA
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| D | phy-mvebu.txt | 1 * Marvell MVEBU SATA PHY
3 Power control for the SATA phy found on Marvell MVEBU SoCs.
5 This document extends the binding described in phy-bindings.txt
9 - reg : Offset and length of the register set for the SATA device
10 - compatible : Should be "marvell,mvebu-sata-phy"
11 - clocks : phandle of clock and specifier that supplies the device
12 - clock-names : Should be "sata"
15 sata-phy@84000 {
16 compatible = "marvell,mvebu-sata-phy";
19 clock-names = "sata";
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| D | berlin-sata-phy.txt | 1 Berlin SATA PHY
2 ---------------
5 - compatible: should be one of
6 "marvell,berlin2-sata-phy"
7 "marvell,berlin2q-sata-phy"
8 - address-cells: should be 1
9 - size-cells: should be 0
10 - phy-cells: from the generic PHY bindings, must be 1
11 - reg: address and length of the register
12 - clocks: reference to the clock entry
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| D | nvidia,tegra124-xusb-padctl.txt | 11 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
12 super-speed USB. Other lanes are for various types of low-speed, full-speed
13 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
14 contains a software-configurable mux that sits between the I/O controller
17 In addition to per-lane configuration, USB 3.0 ports may require additional
18 settings on a per-board basis.
20 Pads will be represented as children of the top-level XUSB pad controller
23 PHY bindings, as described by the phy-bindings.txt file in this directory.
29 abstraction of the signals that are routed to a USB receptacle (i.e. a PHY
34 --------------------
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| D | phy-miphy28lp.txt | 1 STMicroelectronics STi MIPHY28LP PHY binding
4 This binding describes a miphy device that is used to control PHY hardware
5 for SATA, PCIe or USB3.
8 - compatible : Should be "st,miphy28lp-phy".
9 - st,syscfg : Should be a phandle of the system configuration register group
10 which contain the SATA, PCIe or USB3 mode setting bits.
12 Required nodes : A sub-node is required for each channel the controller
14 'reg' and 'reg-names' properties are used inside these
19 - #phy-cells : Should be 1 (See second example)
21 - PHY_TYPE_SATA
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| D | samsung,exynos5250-sata-phy.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/samsung,exynos5250-sata-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung Exynos5250 SoC SATA PHY
10 - Krzysztof Kozlowski <krzk@kernel.org>
11 - Marek Szyprowski <m.szyprowski@samsung.com>
12 - Sylwester Nawrocki <s.nawrocki@samsung.com>
16 const: samsung,exynos5250-sata-phy
21 clock-names:
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| D | hix5hd2-phy.txt | 1 Hisilicon hix5hd2 SATA PHY
2 -----------------------
5 - compatible: should be "hisilicon,hix5hd2-sata-phy"
6 - reg: offset and length of the PHY registers
7 - #phy-cells: must be 0
8 Refer to phy/phy-bindings.txt for the generic PHY binding properties
11 - hisilicon,peripheral-syscon: phandle of syscon used to control peripheral.
12 - hisilicon,power-reg: offset and bit number within peripheral-syscon,
13 register of controlling sata power supply.
16 sata_phy: phy@f9900000 {
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| D | calxeda-combophy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/calxeda-combophy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Calxeda Highbank Combination PHYs binding for SATA
11 and to SATA connectors. The PHYs support multiple protocols (SATA,
12 SGMII, PCIe) and can be assigned to different devices (SATA or XGMAC
15 not by a dedicated PHY driver.
18 - Andre Przywara <andre.przywara@arm.com>
22 const: calxeda,hb-combophy
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| /Linux-v6.1/Documentation/devicetree/bindings/ata/ |
| D | apm-xgene.txt | 1 * APM X-Gene 6.0 Gb/s SATA host controller nodes
3 SATA host controller nodes are defined to describe on-chip Serial ATA
4 controllers. Each SATA controller (pair of ports) have its own node.
7 - compatible : Shall contain:
8 * "apm,xgene-ahci"
9 - reg : First memory resource shall be the AHCI memory
19 - interrupts : Interrupt-specifier for SATA host controller IRQ.
20 - clocks : Reference to the clock entry.
21 - phys : A list of phandles + phy-specifiers, one for each
22 entry in phy-names.
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| D | ahci-common.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/ata/ahci-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Hans de Goede <hdegoede@redhat.com>
11 - Damien Le Moal <damien.lemoal@opensource.wdc.com>
14 This document defines device tree properties for a common AHCI SATA
18 document doesn't constitute a DT-node binding by itself but merely
19 defines a set of common properties for the AHCI-compatible devices.
24 - $ref: sata-common.yaml#
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| D | qcom-sata.txt | 1 * Qualcomm AHCI SATA Controller
3 SATA nodes are defined to describe on-chip Serial ATA controllers.
4 Each SATA controller should have its own node.
7 - compatible : compatible list, must contain "generic-ahci"
8 - interrupts : <interrupt mapping for SATA IRQ>
9 - reg : <registers mapping>
10 - phys : Must contain exactly one entry as specified
11 in phy-bindings.txt
12 - phy-names : Must be "sata-phy"
14 Required properties for "qcom,ipq806x-ahci" compatible:
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| D | ahci-mtk.txt | 4 - compatible : Must be "mediatek,<chip>-ahci", "mediatek,mtk-ahci".
5 When using "mediatek,mtk-ahci" compatible strings, you
7 - "mediatek,mt7622-ahci"
8 - reg : Physical base addresses and length of register sets.
9 - interrupts : Interrupt associated with the SATA device.
10 - interrupt-names : Associated name must be: "hostc".
11 - clocks : A list of phandle and clock specifier pairs, one for each
12 entry in clock-names.
13 - clock-names : Associated names must be: "ahb", "axi", "asic", "rbc", "pm".
14 - phys : A phandle and PHY specifier pair for the PHY port.
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| D | marvell.txt | 1 * Marvell Orion SATA
4 - compatibility : "marvell,orion-sata" or "marvell,armada-370-sata"
5 - reg : Address range of controller
6 - interrupts : Interrupt controller is using
7 - nr-ports : Number of SATA ports in use.
10 - phys : List of phandles to sata phys
11 - phy-names : Should be "0", "1", etc, one number per phandle
15 sata@80000 {
16 compatible = "marvell,orion-sata";
20 phy-names = "0", "1";
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| D | ahci-st.txt | 1 STMicroelectronics STi SATA controller
3 This binding describes a SATA device.
6 - compatible : Must be "st,ahci"
7 - reg : Physical base addresses and length of register sets
8 - interrupts : Interrupt associated with the SATA device
9 - interrupt-names : Associated name must be; "hostc"
10 - clocks : The phandle for the clock
11 - clock-names : Associated name must be; "ahci_clk"
12 - phys : The phandle for the PHY port
13 - phy-names : Associated name must be; "ahci_phy"
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| /Linux-v6.1/drivers/phy/st/ |
| D | phy-spear1340-miphy.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * ST spear1340-miphy driver
12 #include <linux/dma-mapping.h>
17 #include <linux/phy/phy.h>
32 /* PCIE - SATA configuration registers */
75 SATA, enumerator
80 /* phy mode: 0 for SATA 1 for PCIe */
84 /* phy struct pointer */
85 struct phy *phy; member
90 regmap_update_bits(priv->misc, SPEAR1340_PCIE_SATA_CFG, in spear1340_miphy_sata_init()
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| /Linux-v6.1/drivers/phy/samsung/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
3 # Phy drivers for Samsung platforms
6 tristate "Exynos SoC series Display Port PHY driver"
12 Support for Display Port PHY found on Samsung Exynos SoCs.
15 tristate "S5P/Exynos SoC series MIPI CSI-2/DSI PHY driver"
21 Support for MIPI CSI-2 and MIPI DSI DPHY found on Samsung S5P
25 bool "Exynos PCIe PHY driver"
29 Enable PCIe PHY support for Exynos SoC series.
30 This driver provides PHY interface for Exynos PCIe controller.
33 tristate "Exynos SoC series UFS PHY driver"
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| /Linux-v6.1/drivers/phy/marvell/ |
| D | phy-mvebu-sata.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * phy-mvebu-sata.c: SATA Phy driver for the Marvell mvebu SoCs.
11 #include <linux/phy/phy.h>
28 static int phy_mvebu_sata_power_on(struct phy *phy) in phy_mvebu_sata_power_on() argument
30 struct priv *priv = phy_get_drvdata(phy); in phy_mvebu_sata_power_on()
33 clk_prepare_enable(priv->clk); in phy_mvebu_sata_power_on()
36 reg = readl(priv->base + SATA_PHY_MODE_2); in phy_mvebu_sata_power_on()
39 writel(reg , priv->base + SATA_PHY_MODE_2); in phy_mvebu_sata_power_on()
41 /* Enable PHY */ in phy_mvebu_sata_power_on()
42 reg = readl(priv->base + SATA_IF_CTRL); in phy_mvebu_sata_power_on()
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| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
3 # Phy drivers for Marvell platforms
6 bool "Armada 375 USB cluster PHY support" if COMPILE_TEST
12 tristate "Marvell Berlin SATA PHY driver"
17 Enable this to support the SATA PHY on Marvell Berlin SoCs.
20 tristate "Marvell Berlin USB PHY Driver"
25 Enable this to support the USB PHY on Marvell Berlin SoCs.
37 used by various controllers: Ethernet, SATA, USB3, PCIe.
46 Enable this to support Marvell A3700 UTMI PHY driver.
56 used by various controllers (Ethernet, sata, usb, PCIe...).
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| D | phy-berlin-sata.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Marvell Berlin SATA PHY driver
7 * Antoine Ténart <antoine.tenart@free-electrons.com>
12 #include <linux/phy/phy.h>
51 struct phy *phy; member
80 static int phy_berlin_sata_power_on(struct phy *phy) in phy_berlin_sata_power_on() argument
82 struct phy_berlin_desc *desc = phy_get_drvdata(phy); in phy_berlin_sata_power_on()
83 struct phy_berlin_priv *priv = dev_get_drvdata(phy->dev.parent); in phy_berlin_sata_power_on()
84 void __iomem *ctrl_reg = priv->base + 0x60 + (desc->index * 0x80); in phy_berlin_sata_power_on()
87 clk_prepare_enable(priv->clk); in phy_berlin_sata_power_on()
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| /Linux-v6.1/drivers/phy/tegra/ |
| D | xusb-tegra124.c | 1 // SPDX-License-Identifier: GPL-2.0-only
11 #include <linux/phy/phy.h>
229 mutex_lock(&padctl->lock); in tegra124_xusb_padctl_enable()
231 if (padctl->enable++ > 0) in tegra124_xusb_padctl_enable()
251 mutex_unlock(&padctl->lock); in tegra124_xusb_padctl_enable()
259 mutex_lock(&padctl->lock); in tegra124_xusb_padctl_disable()
261 if (WARN_ON(padctl->enable == 0)) in tegra124_xusb_padctl_disable()
264 if (--padctl->enable > 0) in tegra124_xusb_padctl_disable()
284 mutex_unlock(&padctl->lock); in tegra124_xusb_padctl_disable()
297 return -ENODEV; in tegra124_usb3_save_context()
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| /Linux-v6.1/drivers/scsi/mvsas/ |
| D | mv_defs.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
7 * Copyright 2009-2011 Marvell. <yuxiangl@marvell.com>
28 /* driver compile-time configuration */
30 MVS_TX_RING_SZ = 1024, /* TX ring size (12-bit) */
31 MVS_RX_RING_SZ = 1024, /* RX ring size (12-bit) */
32 /* software requires power-of-2
40 MVS_ATA_CMD_SZ = 96, /* SATA command table buffer size */
43 MVS_SOC_CAN_QUEUE = MVS_SOC_SLOTS - 2,
76 INT_SAS_SATA = (1U << 0), /* SAS/SATA event */
78 /* MVS_GBL_PORT_TYPE */ /* shl for ports 1-3 */
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| /Linux-v6.1/drivers/phy/qualcomm/ |
| D | phy-qcom-apq8064-sata.c | 1 // SPDX-License-Identifier: GPL-2.0-only
16 #include <linux/phy/phy.h>
18 /* PHY registers */
84 static int qcom_apq8064_sata_phy_init(struct phy *generic_phy) in qcom_apq8064_sata_phy_init()
86 struct qcom_apq8064_sata_phy *phy = phy_get_drvdata(generic_phy); in qcom_apq8064_sata_phy_init() local
87 void __iomem *base = phy->mmio; in qcom_apq8064_sata_phy_init()
90 /* SATA phy initialization */ in qcom_apq8064_sata_phy_init()
137 dev_err(phy->dev, "poll timeout UNIPHY_PLL_STATUS\n"); in qcom_apq8064_sata_phy_init()
144 dev_err(phy->dev, "poll timeout SATA_PHY_TX_IMCAL_STAT\n"); in qcom_apq8064_sata_phy_init()
151 dev_err(phy->dev, "poll timeout SATA_PHY_RX_IMCAL_STAT\n"); in qcom_apq8064_sata_phy_init()
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