Searched +full:rzg2l +full:- +full:pinctrl (Results 1 – 23 of 23) sorted by relevance
/Linux-v6.6/Documentation/devicetree/bindings/pinctrl/ |
D | renesas,rzg2l-pinctrl.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/pinctrl/renesas,rzg2l-pinctrl.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Geert Uytterhoeven <geert+renesas@glider.be> 11 - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> 16 Pin multiplexing and GPIO configuration is performed on a per-pin basis. 24 - items: 25 - enum: 26 - renesas,r9a07g043-pinctrl # RZ/G2UL{Type-1,Type-2} and RZ/Five [all …]
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D | renesas,rzg2l-poeg.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/pinctrl/renesas,rzg2l-poeg.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Biju Das <biju.das.jz@bp.renesas.com> 17 * Output-disable request from the GPT. 26 - enum: 27 - renesas,r9a07g044-poeg # RZ/G2{L,LC} 28 - renesas,r9a07g054-poeg # RZ/V2L 29 - const: renesas,rzg2l-poeg [all …]
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/Linux-v6.6/arch/arm64/boot/dts/renesas/ |
D | r9a07g044c2-smarc-cru-csi-ov5645.dtso | 1 // SPDX-License-Identifier: GPL-2.0 9 /dts-v1/; 12 #include <dt-bindings/gpio/gpio.h> 13 #include <dt-bindings/pinctrl/rzg2l-pinctrl.h> 16 #include "rz-smarc-cru-csi-ov5645.dtsi" 19 enable-gpios = <&pinctrl RZG2L_GPIO(0, 1) GPIO_ACTIVE_HIGH>; 20 reset-gpios = <&pinctrl RZG2L_GPIO(5, 2) GPIO_ACTIVE_LOW>;
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D | r9a07g044l2-smarc-cru-csi-ov5645.dtso | 1 // SPDX-License-Identifier: GPL-2.0 9 /dts-v1/; 12 #include <dt-bindings/gpio/gpio.h> 13 #include <dt-bindings/pinctrl/rzg2l-pinctrl.h> 16 #include "rz-smarc-cru-csi-ov5645.dtsi" 19 enable-gpios = <&pinctrl RZG2L_GPIO(2, 0) GPIO_ACTIVE_HIGH>; 20 reset-gpios = <&pinctrl RZG2L_GPIO(40, 2) GPIO_ACTIVE_LOW>;
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D | r9a07g054l2-smarc-cru-csi-ov5645.dtso | 1 // SPDX-License-Identifier: GPL-2.0 9 /dts-v1/; 12 #include <dt-bindings/gpio/gpio.h> 13 #include <dt-bindings/pinctrl/rzg2l-pinctrl.h> 16 #include "rz-smarc-cru-csi-ov5645.dtsi" 19 enable-gpios = <&pinctrl RZG2L_GPIO(2, 0) GPIO_ACTIVE_HIGH>; 20 reset-gpios = <&pinctrl RZG2L_GPIO(40, 2) GPIO_ACTIVE_LOW>;
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D | r9a07g043-smarc-pmod.dtso | 1 // SPDX-License-Identifier: GPL-2.0 11 * +----------------------------+ 17 * +----------------------------+ 21 /dts-v1/; 24 #include <dt-bindings/pinctrl/rzg2l-pinctrl.h> 26 &pinctrl { 27 can0-stb-hog { 31 can1-stb-hog { 35 sci0_pins: sci0-pins { 42 pinctrl-0 = <&sci0_pins>; [all …]
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D | rzg2ul-smarc-som.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 8 #include <dt-bindings/gpio/gpio.h> 9 #include <dt-bindings/interrupt-controller/irqc-rzg2l.h> 10 #include <dt-bindings/pinctrl/rzg2l-pinctrl.h> 28 reg_1p8v: regulator-1p8v { 29 compatible = "regulator-fixed"; 30 regulator-name = "fixed-1.8V"; 31 regulator-min-microvolt = <1800000>; 32 regulator-max-microvolt = <1800000>; 33 regulator-boot-on; [all …]
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D | rzg2lc-smarc-som.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 8 #include <dt-bindings/gpio/gpio.h> 9 #include <dt-bindings/interrupt-controller/irqc-rzg2l.h> 10 #include <dt-bindings/pinctrl/rzg2l-pinctrl.h> 27 reg_1p8v: regulator-1p8v { 28 compatible = "regulator-fixed"; 29 regulator-name = "fixed-1.8V"; 30 regulator-min-microvolt = <1800000>; 31 regulator-max-microvolt = <1800000>; 32 regulator-boot-on; [all …]
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D | r9a07g054.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 8 #include <dt-bindings/interrupt-controller/arm-gic.h> 9 #include <dt-bindings/clock/r9a07g054-cpg.h> 13 #address-cells = <2>; 14 #size-cells = <2>; 16 audio_clk1: audio1-clk { 17 compatible = "fixed-clock"; 18 #clock-cells = <0>; 20 clock-frequency = <0>; 23 audio_clk2: audio2-clk { [all …]
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D | r9a07g043.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 8 #include <dt-bindings/clock/r9a07g043-cpg.h> 12 #address-cells = <2>; 13 #size-cells = <2>; 15 audio_clk1: audio1-clk { 16 compatible = "fixed-clock"; 17 #clock-cells = <0>; 19 clock-frequency = <0>; 22 audio_clk2: audio2-clk { 23 compatible = "fixed-clock"; [all …]
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D | r9a07g044.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 8 #include <dt-bindings/interrupt-controller/arm-gic.h> 9 #include <dt-bindings/clock/r9a07g044-cpg.h> 13 #address-cells = <2>; 14 #size-cells = <2>; 16 audio_clk1: audio1-clk { 17 compatible = "fixed-clock"; 18 #clock-cells = <0>; 20 clock-frequency = <0>; 23 audio_clk2: audio2-clk { [all …]
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D | rzg2l-smarc.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 8 #include <dt-bindings/gpio/gpio.h> 9 #include <dt-bindings/pinctrl/rzg2l-pinctrl.h> 17 osc1: cec-clock { 18 compatible = "fixed-clock"; 19 #clock-cells = <0>; 20 clock-frequency = <12000000>; 23 hdmi-out { 24 compatible = "hdmi-connector"; 29 remote-endpoint = <&adv7535_out>; [all …]
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D | rzg2l-smarc-som.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 8 #include <dt-bindings/gpio/gpio.h> 9 #include <dt-bindings/interrupt-controller/irqc-rzg2l.h> 10 #include <dt-bindings/pinctrl/rzg2l-pinctrl.h> 38 reg_1p8v: regulator-1p8v { 39 compatible = "regulator-fixed"; 40 regulator-name = "fixed-1.8V"; 41 regulator-min-microvolt = <1800000>; 42 regulator-max-microvolt = <1800000>; 43 regulator-boot-on; [all …]
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D | rz-smarc-common.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 8 #include <dt-bindings/gpio/gpio.h> 9 #include <dt-bindings/pinctrl/rzg2l-pinctrl.h> 12 * SSI-WM8978 32 stdout-path = "serial0:115200n8"; 36 compatible = "fixed-clock"; 37 #clock-cells = <0>; 38 clock-frequency = <11289600>; 42 compatible = "simple-audio-card"; 43 simple-audio-card,format = "i2s"; [all …]
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D | rzg2lc-smarc.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 8 #include <dt-bindings/gpio/gpio.h> 9 #include <dt-bindings/pinctrl/rzg2l-pinctrl.h> 11 #include "rzg2lc-smarc-pinfunction.dtsi" 12 #include "rz-smarc-common.dtsi" 20 osc1: cec-clock { 21 compatible = "fixed-clock"; 22 #clock-cells = <0>; 23 clock-frequency = <12000000>; 26 hdmi-out { [all …]
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D | rzg2ul-smarc-pinfunction.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 8 #include <dt-bindings/gpio/gpio.h> 9 #include <dt-bindings/pinctrl/rzg2l-pinctrl.h> 11 &pinctrl { 12 pinctrl-0 = <&sound_clk_pins>; 13 pinctrl-names = "default"; 21 can0-stb-hog { 22 gpio-hog; 24 output-low; 25 line-name = "can0_stb"; [all …]
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D | rzg2lc-smarc-pinfunction.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 8 #include <dt-bindings/gpio/gpio.h> 9 #include <dt-bindings/pinctrl/rzg2l-pinctrl.h> 11 &pinctrl { 12 pinctrl-0 = <&sound_clk_pins>; 13 pinctrl-names = "default"; 16 /* SW8 should be at position 2->1 */ 24 /* SW8 should be at position 2->3 so that GPIO9_CAN1_STB line is activated */ 25 can1-stb-hog { 26 gpio-hog; [all …]
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D | rzg2l-smarc-pinfunction.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 8 #include <dt-bindings/gpio/gpio.h> 9 #include <dt-bindings/pinctrl/rzg2l-pinctrl.h> 11 &pinctrl { 12 pinctrl-0 = <&sound_clk_pins>; 13 pinctrl-names = "default"; 20 /* SW7 should be at position 2->3 so that GPIO8_CAN0_STB line is activated */ 21 can0-stb-hog { 22 gpio-hog; 24 output-low; [all …]
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D | r9a07g043u.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 8 #include <dt-bindings/interrupt-controller/arm-gic.h> 16 #address-cells = <1>; 17 #size-cells = <0>; 20 compatible = "arm,cortex-a55"; 23 #cooling-cells = <2>; 24 next-level-cache = <&L3_CA55>; 25 enable-method = "psci"; 27 operating-points-v2 = <&cluster0_opp>; 30 L3_CA55: cache-controller-0 { [all …]
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/Linux-v6.6/drivers/pinctrl/renesas/ |
D | Makefile | 1 # SPDX-License-Identifier: GPL-2.0 2 obj-$(CONFIG_PINCTRL_SH_PFC) += core.o pinctrl.o 3 obj-$(CONFIG_PINCTRL_SH_PFC_GPIO) += gpio.o 4 obj-$(CONFIG_PINCTRL_PFC_EMEV2) += pfc-emev2.o 5 obj-$(CONFIG_PINCTRL_PFC_R8A73A4) += pfc-r8a73a4.o 6 obj-$(CONFIG_PINCTRL_PFC_R8A7740) += pfc-r8a7740.o 7 obj-$(CONFIG_PINCTRL_PFC_R8A7742) += pfc-r8a7790.o 8 obj-$(CONFIG_PINCTRL_PFC_R8A7743) += pfc-r8a7791.o 9 obj-$(CONFIG_PINCTRL_PFC_R8A7744) += pfc-r8a7791.o 10 obj-$(CONFIG_PINCTRL_PFC_R8A7745) += pfc-r8a7794.o [all …]
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D | pinctrl-rzg2l.c | 1 // SPDX-License-Identifier: GPL-2.0 21 #include <linux/pinctrl/consumer.h> 22 #include <linux/pinctrl/pinconf-generic.h> 23 #include <linux/pinctrl/pinconf.h> 24 #include <linux/pinctrl/pinctrl.h> 25 #include <linux/pinctrl/pinmux.h> 27 #include <dt-bindings/pinctrl/rzg2l-pinctrl.h> 33 #define DRV_NAME "pinctrl-rzg2l" 169 spin_lock_irqsave(&pctrl->lock, flags); in rzg2l_pinctrl_set_pfc_mode() 171 /* Set pin to 'Non-use (Hi-Z input protection)' */ in rzg2l_pinctrl_set_pfc_mode() [all …]
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/Linux-v6.6/drivers/irqchip/ |
D | irq-renesas-rzg2l.c | 1 // SPDX-License-Identifier: GPL-2.0 7 * Author: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> 67 return data->domain->host_data; in irq_data_to_priv() 72 unsigned int hw_irq = irqd_to_hwirq(d) - IRQC_IRQ_START; in rzg2l_irq_eoi() 77 reg = readl_relaxed(priv->base + ISCR); in rzg2l_irq_eoi() 79 writel_relaxed(reg & ~bit, priv->base + ISCR); in rzg2l_irq_eoi() 84 unsigned int hw_irq = irqd_to_hwirq(d) - IRQC_TINT_START; in rzg2l_tint_eoi() 89 reg = readl_relaxed(priv->base + TSCR); in rzg2l_tint_eoi() 91 writel_relaxed(reg & ~bit, priv->base + TSCR); in rzg2l_tint_eoi() 99 raw_spin_lock(&priv->lock); in rzg2l_irqc_eoi() [all …]
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/Linux-v6.6/ |
D | MAINTAINERS | 5 --------------------------------------------------- 21 W: *Web-page* with status/info 23 B: URI for where to file *bugs*. A web-page with detailed bug 28 patches to the given subsystem. This is either an in-tree file, 29 or a URI. See Documentation/maintainer/maintainer-entry-profile.rst 46 N: [^a-z]tegra all files whose path contains tegra 64 ---------------- 83 3WARE SAS/SATA-RAID SCSI DRIVERS (3W-XXXX, 3W-9XXX, 3W-SAS) 85 L: linux-scsi@vger.kernel.org 88 F: drivers/scsi/3w-* [all …]
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