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/Linux-v5.15/Documentation/devicetree/bindings/interrupt-controller/
Drealtek,rtl-intc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/realtek,rtl-intc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Realtek RTL SoC interrupt controller devicetree bindings
10 - Birger Koblitz <mail@birger-koblitz.de>
11 - Bert Vermeulen <bert@biot.com>
12 - John Crispin <john@phrozen.org>
16 const: realtek,rtl-intc
18 "#interrupt-cells":
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/Linux-v5.15/drivers/irqchip/
Dirq-realtek-rtl.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2020 Birger Koblitz <mail@birger-koblitz.de>
37 value |= BIT(i->hwirq); in realtek_ictl_unmask_irq()
51 value &= ~BIT(i->hwirq); in realtek_ictl_mask_irq()
58 .name = "realtek-rtl-intc",
96 * interrupt-map in the device tree. Each SoC interrupt gets 4 bits for
113 ret = of_property_read_u32(node, "#address-cells", &tmp); in map_interrupts()
115 return -EINVAL; in map_interrupts()
117 imap = of_get_property(node, "interrupt-map", &imaplen); in map_interrupts()
119 return -EINVAL; in map_interrupts()
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DMakefile1 # SPDX-License-Identifier: GPL-2.0
2 obj-$(CONFIG_IRQCHIP) += irqchip.o
4 obj-$(CONFIG_AL_FIC) += irq-al-fic.o
5 obj-$(CONFIG_ALPINE_MSI) += irq-alpine-msi.o
6 obj-$(CONFIG_ATH79) += irq-ath79-cpu.o
7 obj-$(CONFIG_ATH79) += irq-ath79-misc.o
8 obj-$(CONFIG_ARCH_BCM2835) += irq-bcm2835.o
9 obj-$(CONFIG_ARCH_BCM2835) += irq-bcm2836.o
10 obj-$(CONFIG_ARCH_ACTIONS) += irq-owl-sirq.o
11 obj-$(CONFIG_DAVINCI_AINTC) += irq-davinci-aintc.o
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/Linux-v5.15/arch/arc/plat-hsdk/
Dplatform.c1 // SPDX-License-Identifier: GPL-2.0-only
33 * Peripherals on CPU Card are wired to cpu intc via intermediate in hsdk_enable_gpio_intc_wire()
36 * --------------------- in hsdk_enable_gpio_intc_wire()
37 * | snps,archs-intc | in hsdk_enable_gpio_intc_wire()
38 * --------------------- in hsdk_enable_gpio_intc_wire()
40 * ---------------------- in hsdk_enable_gpio_intc_wire()
41 * | snps,archs-idu-intc | in hsdk_enable_gpio_intc_wire()
42 * ---------------------- in hsdk_enable_gpio_intc_wire()
46 * ------------------- in hsdk_enable_gpio_intc_wire()
47 * | snps,dw-apb-intc | in hsdk_enable_gpio_intc_wire()
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/Linux-v5.15/arch/sh/kernel/
Dhead_32.S1 /* SPDX-License-Identifier: GPL-2.0
42 .skip PAGE_SIZE - empty_zero_page - 1b
50 * INTC may or may not be initialized.
54 * Hardware (including on-chip modules) may or may not be initialized.
74 * We do this early on for SH-4A as a micro-optimization,
93 * When we boot in 32-bit MMU mode there are 2 PMB entries already
97 * ---------------------------------------------------------------
117 * mapping are unsupported in 32-bit mode and must specify their caching
296 * Don't clear BSS if running on slow platforms such as an RTL simulation,
313 mov.l r0,@-r2
/Linux-v5.15/drivers/net/dsa/
Drtl8366rb.c1 // SPDX-License-Identifier: GPL-2.0
9 * Copyright (C) 2009-2010 Gabor Juhos <juhosg@openwrt.org>
23 #include "realtek-smi-core.h"
315 * struct rtl8366rb - RTL8366RB-specific data
316 * @max_mtu: per-port max MTU setting
369 mib->offset; in rtl8366rb_get_mib_counter()
374 ret = regmap_write(smi->map, addr, 0); /* Write whatever */ in rtl8366rb_get_mib_counter()
379 ret = regmap_read(smi->map, RTL8366RB_MIB_CTRL_REG, &val); in rtl8366rb_get_mib_counter()
381 return -EIO; in rtl8366rb_get_mib_counter()
384 return -EBUSY; in rtl8366rb_get_mib_counter()
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