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Searched +full:rockchip +full:- +full:dp +full:- +full:phy (Results 1 – 16 of 16) sorted by relevance

/Linux-v6.1/drivers/phy/rockchip/
Dphy-rockchip-dp.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Rockchip DP PHY driver
5 * Copyright (C) 2016 FuZhou Rockchip Co., Ltd.
6 * Author: Yakir Yang <ykk@@rock-chips.com>
13 #include <linux/phy/phy.h>
32 static int rockchip_set_phy_state(struct phy *phy, bool enable) in rockchip_set_phy_state() argument
34 struct rockchip_dp_phy *dp = phy_get_drvdata(phy); in rockchip_set_phy_state() local
38 ret = regmap_write(dp->grf, GRF_SOC_CON12, in rockchip_set_phy_state()
42 dev_err(dp->dev, "Can't enable PHY power %d\n", ret); in rockchip_set_phy_state()
46 ret = clk_prepare_enable(dp->phy_24m); in rockchip_set_phy_state()
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DMakefile1 # SPDX-License-Identifier: GPL-2.0
2 obj-$(CONFIG_PHY_ROCKCHIP_DP) += phy-rockchip-dp.o
3 obj-$(CONFIG_PHY_ROCKCHIP_DPHY_RX0) += phy-rockchip-dphy-rx0.o
4 obj-$(CONFIG_PHY_ROCKCHIP_EMMC) += phy-rockchip-emmc.o
5 obj-$(CONFIG_PHY_ROCKCHIP_INNO_CSIDPHY) += phy-rockchip-inno-csidphy.o
6 obj-$(CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY) += phy-rockchip-inno-dsidphy.o
7 obj-$(CONFIG_PHY_ROCKCHIP_INNO_HDMI) += phy-rockchip-inno-hdmi.o
8 obj-$(CONFIG_PHY_ROCKCHIP_INNO_USB2) += phy-rockchip-inno-usb2.o
9 obj-$(CONFIG_PHY_ROCKCHIP_NANENG_COMBO_PHY) += phy-rockchip-naneng-combphy.o
10 obj-$(CONFIG_PHY_ROCKCHIP_PCIE) += phy-rockchip-pcie.o
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Dphy-rockchip-typec.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
4 * Author: Chris Zhong <zyw@rock-chips.com>
5 * Kever Yang <kever.yang@rock-chips.com>
7 * The ROCKCHIP Type-C PHY has two PLL clocks. The first PLL clock
8 * is used for USB3, the second PLL clock is used for DP. This Type-C PHY has
9 * 3 working modes: USB3 only mode, DP only mode, and USB3+DP mode.
11 * PHY to switch mode between USB3 and USB3+DP, without disconnecting the USB
13 * In The DP only mode, only the DP PLL needs to be powered on, and the 4 lanes
14 * are all used for DP.
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Dphy-rockchip-inno-usb2.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Rockchip USB2.0 PHY with Innosilicon IP block driver
5 * Copyright (C) 2016 Fuzhou Rockchip Electronics Co., Ltd
9 #include <linux/clk-provider.h>
11 #include <linux/extcon-provider.h>
23 #include <linux/phy/phy.h>
49 * enum usb_chg_state - Different states involved in USB charger detection.
88 * struct rockchip_chg_det_reg - usb charger detect registers
93 * @idp_sink_en: open dp sink current.
97 * @vdp_src_en: open dp voltage source.
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/Linux-v6.1/Documentation/devicetree/bindings/phy/
Dphy-rockchip-typec.txt1 * ROCKCHIP type-c PHY
2 ---------------------
5 - compatible : must be "rockchip,rk3399-typec-phy"
6 - reg: Address and length of the usb phy control register set
7 - rockchip,grf : phandle to the syscon managing the "general
9 - clocks : phandle + clock specifier for the phy clocks
10 - clock-names : string, clock name, must be "tcpdcore", "tcpdphy-ref";
11 - assigned-clocks: main clock, should be <&cru SCLK_UPHY0_TCPDCORE> or
13 - assigned-clock-rates : the phy core clk frequency, shall be: 50000000
14 - resets : a list of phandle + reset specifier pairs
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Drockchip-dp-phy.txt1 Rockchip specific extensions to the Analogix Display Port PHY
2 ------------------------------------
5 - compatible : should be one of the following supported values:
6 - "rockchip.rk3288-dp-phy"
7 - clocks: from common clock binding: handle to dp clock.
9 - clock-names: from common clock binding:
11 - #phy-cells : from the generic PHY bindings, must be 0;
16 compatible = "rockchip,rk3288-grf", "syscon", "simple-mfd";
20 edp_phy: edp-phy {
21 compatible = "rockchip,rk3288-dp-phy";
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/Linux-v6.1/Documentation/devicetree/bindings/display/bridge/
Danalogix_dp.txt3 Required properties for dp-controller:
4 -compatible:
6 * "samsung,exynos5-dp"
7 * "rockchip,rk3288-dp"
8 * "rockchip,rk3399-edp"
9 -reg:
12 -interrupts:
14 -clocks:
15 from common clock binding: handle to dp clock.
16 -clock-names:
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/Linux-v6.1/Documentation/devicetree/bindings/display/rockchip/
Danalogix_dp-rockchip.txt1 Rockchip RK3288 specific extensions to the Analogix Display Port
5 - compatible: "rockchip,rk3288-dp",
6 "rockchip,rk3399-edp";
8 - reg: physical base address of the controller and length
10 - clocks: from common clock binding: handle to dp clock.
13 - clock-names: from common clock binding:
14 Required elements: "dp" "pclk"
16 - resets: Must contain an entry for each entry in reset-names.
19 - pinctrl-names: Names corresponding to the chip hotplug pinctrl states.
20 - pinctrl-0: pin-control mode. should be <&edp_hpd>
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Dcdn-dp-rockchip.txt1 Rockchip RK3399 specific extensions to the cdn Display Port
5 - compatible: must be "rockchip,rk3399-cdn-dp"
7 - reg: physical base address of the controller and length
9 - clocks: from common clock binding: handle to dp clock.
11 - clock-names: from common clock binding:
12 Required elements: "core-clk" "pclk" "spdif" "grf"
14 - resets : a list of phandle + reset specifier pairs
15 - reset-names : string of reset names
17 - power-domains : power-domain property defined with a phandle
19 - assigned-clocks: main clock, should be <&cru SCLK_DP_CORE>
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/Linux-v6.1/Documentation/devicetree/bindings/soc/rockchip/
Dgrf.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/soc/rockchip/grf.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip General Register Files (GRF)
10 - Heiko Stuebner <heiko@sntech.de>
15 - items:
16 - enum:
17 - rockchip,rk3288-sgrf
18 - rockchip,rk3566-pipe-grf
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/Linux-v6.1/drivers/gpu/drm/rockchip/
Dcdn-dp-core.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
4 * Author: Chris Zhong <zyw@rock-chips.com>
12 #include <linux/phy/phy.h>
16 #include <sound/hdmi-codec.h>
25 #include "cdn-dp-core.h"
26 #include "cdn-dp-reg.h"
50 #define CDN_DP_FIRMWARE "rockchip/dptx.bin"
62 { .compatible = "rockchip,rk3399-cdn-dp",
69 static int cdn_dp_grf_write(struct cdn_dp_device *dp, in cdn_dp_grf_write() argument
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Dcdn-dp-core.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) 2016 Chris Zhong <zyw@rock-chips.com>
4 * Copyright (C) 2016 ROCKCHIP, Inc.
13 #include <sound/hdmi-codec.h>
56 struct cdn_dp_device *dp; member
59 struct phy *phy; member
80 const struct firmware *fw; /* cdn dp firmware */
Dcdn-dp-reg.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
4 * Author: Chris Zhong <zyw@rock-chips.com>
114 /* dptx phy addr */
175 /* dp aux addr */
400 #define MAX_NUM_CH(x) (((x) & 0x1f) - 1)
401 #define NUM_OF_I2S_PORTS(x) ((((x) / 2 - 1) & 0x3) << 5)
403 #define CFG_SUB_PCKT_NUM(x) ((((x) - 1) & 0x7) << 11)
404 #define AUDIO_CH_NUM(x) ((((x) - 1) & 0x1f) << 2)
454 void cdn_dp_clock_reset(struct cdn_dp_device *dp);
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/Linux-v6.1/arch/arm/boot/dts/
Drk3288.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 #include <dt-bindings/gpio/gpio.h>
4 #include <dt-bindings/interrupt-controller/irq.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/pinctrl/rockchip.h>
7 #include <dt-bindings/clock/rk3288-cru.h>
8 #include <dt-bindings/power/rk3288-power.h>
9 #include <dt-bindings/thermal/thermal.h>
10 #include <dt-bindings/soc/rockchip,boot-mode.h>
13 #address-cells = <2>;
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/Linux-v6.1/arch/arm64/boot/dts/rockchip/
Drk3399.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
6 #include <dt-bindings/clock/rk3399-cru.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/power/rk3399-power.h>
12 #include <dt-bindings/thermal/thermal.h>
15 compatible = "rockchip,rk3399";
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/Linux-v6.1/
DMAINTAINERS9 -------------------------
30 ``diff -u`` to make the patch easy to merge. Be prepared to get your
40 See Documentation/process/coding-style.rst for guidance here.
46 See Documentation/process/submitting-patches.rst for details.
57 include a Signed-off-by: line. The current version of this
59 Documentation/process/submitting-patches.rst.
70 that the bug would present a short-term risk to other users if it
76 Documentation/admin-guide/security-bugs.rst for details.
81 ---------------------------------------------------
97 W: *Web-page* with status/info
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