| /Linux-v6.1/Documentation/devicetree/bindings/soc/rockchip/ |
| D | grf.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/soc/rockchip/grf.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip General Register Files (GRF)
10 - Heiko Stuebner <heiko@sntech.de>
15 - items:
16 - enum:
17 - rockchip,rk3288-sgrf
18 - rockchip,rk3566-pipe-grf
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| /Linux-v6.1/Documentation/devicetree/bindings/phy/ |
| D | rockchip-mipi-dphy-rx0.yaml | 1 # SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 ---
4 $id: http://devicetree.org/schemas/phy/rockchip-mipi-dphy-rx0.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip SoC MIPI RX0 D-PHY
10 - Helen Koike <helen.koike@collabora.com>
11 - Ezequiel Garcia <ezequiel@collabora.com>
14 The Rockchip SoC has a MIPI D-PHY bus with an RX0 entry which connects to
19 const: rockchip,rk3399-mipi-dphy-rx0
23 - description: MIPI D-PHY ref clock
[all …]
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| D | phy-rockchip-typec.txt | 1 * ROCKCHIP type-c PHY
2 ---------------------
5 - compatible : must be "rockchip,rk3399-typec-phy"
6 - reg: Address and length of the usb phy control register set
7 - rockchip,grf : phandle to the syscon managing the "general
9 - clocks : phandle + clock specifier for the phy clocks
10 - clock-names : string, clock name, must be "tcpdcore", "tcpdphy-ref";
11 - assigned-clocks: main clock, should be <&cru SCLK_UPHY0_TCPDCORE> or
13 - assigned-clock-rates : the phy core clk frequency, shall be: 50000000
14 - resets : a list of phandle + reset specifier pairs
[all …]
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| D | rockchip-pcie-phy.txt | 2 -----------------------
5 - compatible: rockchip,rk3399-pcie-phy
6 - clocks: Must contain an entry in clock-names.
7 See ../clocks/clock-bindings.txt for details.
8 - clock-names: Must be "refclk"
9 - resets: Must contain an entry in reset-names.
11 - reset-names: Must be "phy"
14 - #phy-cells: must be 0
16 Required properties for per-lane PHY mode (preferred):
17 - #phy-cells: must be 1
[all …]
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| D | rockchip-emmc-phy.txt | 2 -----------------------
5 - compatible: rockchip,rk3399-emmc-phy
6 - #phy-cells: must be 0
7 - reg: PHY register address offset and length in "general
11 - clock-names: Should contain "emmcclk". Although this is listed as optional
14 See ../clock/clock-bindings.txt for details.
15 - clocks: Should have a phandle to the card clock exported by the SDHCI driver.
16 - drive-impedance-ohm: Specifies the drive impedance in Ohm.
19 - rockchip,enable-strobe-pulldown: Enable internal pull-down for the strobe
20 line. If not set, pull-down is not used.
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| D | phy-rockchip-inno-usb2.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/phy/phy-rockchip-inno-usb2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Heiko Stuebner <heiko@sntech.de>
15 - rockchip,px30-usb2phy
16 - rockchip,rk3128-usb2phy
17 - rockchip,rk3228-usb2phy
18 - rockchip,rk3308-usb2phy
19 - rockchip,rk3328-usb2phy
[all …]
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| /Linux-v6.1/Documentation/devicetree/bindings/clock/ |
| D | rockchip,rk3399-cru.yaml | 1 # SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 ---
4 $id: http://devicetree.org/schemas/clock/rockchip,rk3399-cru.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip RK3399 Clock and Reset Unit
10 - Elaine Zhang <zhangqing@rock-chips.com>
11 - Heiko Stuebner <heiko@sntech.de>
14 The RK3399 clock controller generates and supplies clock to various
19 preprocessor macros in the dt-bindings/clock/rk3399-cru.h headers and can be
24 clock-output-names:
[all …]
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| /Linux-v6.1/arch/arm64/boot/dts/rockchip/ |
| D | rk3399.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/rk3399-cru.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/power/rk3399-power.h>
12 #include <dt-bindings/thermal/thermal.h>
15 compatible = "rockchip,rk3399";
17 interrupt-parent = <&gic>;
[all …]
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| D | rk356x.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/rk3568-cru.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/phy/phy.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/power/rk3568-power.h>
12 #include <dt-bindings/soc/rockchip,boot-mode.h>
13 #include <dt-bindings/thermal/thermal.h>
16 interrupt-parent = <&gic>;
[all …]
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| D | rk3328.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/rk3328-cru.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/power/rk3328-power.h>
12 #include <dt-bindings/soc/rockchip,boot-mode.h>
13 #include <dt-bindings/thermal/thermal.h>
18 interrupt-parent = <&gic>;
[all …]
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| /Linux-v6.1/Documentation/devicetree/bindings/display/rockchip/ |
| D | cdn-dp-rockchip.txt | 1 Rockchip RK3399 specific extensions to the cdn Display Port
5 - compatible: must be "rockchip,rk3399-cdn-dp"
7 - reg: physical base address of the controller and length
9 - clocks: from common clock binding: handle to dp clock.
11 - clock-names: from common clock binding:
12 Required elements: "core-clk" "pclk" "spdif" "grf"
14 - resets : a list of phandle + reset specifier pairs
15 - reset-names : string of reset names
17 - power-domains : power-domain property defined with a phandle
19 - assigned-clocks: main clock, should be <&cru SCLK_DP_CORE>
[all …]
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| D | dw_mipi_dsi_rockchip.txt | 5 - #address-cells: Should be <1>.
6 - #size-cells: Should be <0>.
7 - compatible: one of
8 "rockchip,px30-mipi-dsi", "snps,dw-mipi-dsi"
9 "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi"
10 "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi"
11 "rockchip,rk3568-mipi-dsi", "snps,dw-mipi-dsi"
12 - reg: Represent the physical address range of the controller.
13 - interrupts: Represent the controller's interrupt to the CPU(s).
14 - clocks, clock-names: Phandles to the controller's pll reference
[all …]
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| D | analogix_dp-rockchip.txt | 5 - compatible: "rockchip,rk3288-dp",
6 "rockchip,rk3399-edp";
8 - reg: physical base address of the controller and length
10 - clocks: from common clock binding: handle to dp clock.
13 - clock-names: from common clock binding:
16 - resets: Must contain an entry for each entry in reset-names.
19 - pinctrl-names: Names corresponding to the chip hotplug pinctrl states.
20 - pinctrl-0: pin-control mode. should be <&edp_hpd>
22 - reset-names: Must include the name "dp"
24 - rockchip,grf: this soc should set GRF regs, so need get grf here.
[all …]
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| D | rockchip,dw-hdmi.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/rockchip/rockchip,dw-hdmi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Mark Yao <markyao0591@gmail.com>
17 - $ref: ../bridge/synopsys,dw-hdmi.yaml#
22 - rockchip,rk3228-dw-hdmi
23 - rockchip,rk3288-dw-hdmi
24 - rockchip,rk3328-dw-hdmi
25 - rockchip,rk3399-dw-hdmi
[all …]
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| /Linux-v6.1/Documentation/devicetree/bindings/i2c/ |
| D | i2c-rk3x.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/i2c/i2c-rk3x.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
14 - $ref: /schemas/i2c/i2c-controller.yaml#
17 - Heiko Stuebner <heiko@sntech.de>
23 - const: rockchip,rv1108-i2c
24 - const: rockchip,rk3066-i2c
25 - const: rockchip,rk3188-i2c
26 - const: rockchip,rk3228-i2c
[all …]
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| /Linux-v6.1/Documentation/devicetree/bindings/net/ |
| D | rockchip-dwmac.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: "http://devicetree.org/schemas/net/rockchip-dwmac.yaml#"
5 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
10 - David Wu <david.wu@rock-chips.com>
18 - rockchip,px30-gmac
19 - rockchip,rk3128-gmac
20 - rockchip,rk3228-gmac
21 - rockchip,rk3288-gmac
22 - rockchip,rk3308-gmac
[all …]
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| /Linux-v6.1/drivers/soc/rockchip/ |
| D | grf.c | 1 // SPDX-License-Identifier: GPL-2.0-only
33 * clock-framework and the mmc controllers making them unreliable.
127 .compatible = "rockchip,rk3036-grf",
130 .compatible = "rockchip,rk3128-grf",
133 .compatible = "rockchip,rk3228-grf",
136 .compatible = "rockchip,rk3288-grf",
139 .compatible = "rockchip,rk3328-grf",
142 .compatible = "rockchip,rk3368-grf",
145 .compatible = "rockchip,rk3399-grf",
148 .compatible = "rockchip,rk3566-pipe-grf",
[all …]
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| D | io-domain.c | 1 // SPDX-License-Identifier: GPL-2.0-only
26 * - If the voltage on a rail is above the "1.8" voltage (1.98V) we'll tell the
28 * - If the voltage on a rail is above the "3.3" voltage (3.6V) we'll consider
76 struct regmap *grf; member
84 struct rockchip_iodomain *iod = supply->iod; in rk3568_iodomain_write()
89 switch (supply->idx) { in rk3568_iodomain_write()
93 b = supply->idx; in rk3568_iodomain_write()
95 b = supply->idx + 4; in rk3568_iodomain_write()
98 regmap_write(iod->grf, RK3568_PMU_GRF_IO_VSEL2, val0); in rk3568_iodomain_write()
99 regmap_write(iod->grf, RK3568_PMU_GRF_IO_VSEL2, val1); in rk3568_iodomain_write()
[all …]
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| /Linux-v6.1/Documentation/devicetree/bindings/usb/ |
| D | rockchip,dwc3.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Heiko Stuebner <heiko@sntech.de>
18 Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb2.yaml
20 Type-C PHY
21 Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt
24 - $ref: snps,dwc3.yaml#
31 - rockchip,rk3328-dwc3
32 - rockchip,rk3399-dwc3
[all …]
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| /Linux-v6.1/Documentation/devicetree/bindings/sound/ |
| D | rockchip-spdif.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/sound/rockchip-spdif.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
15 - Heiko Stuebner <heiko@sntech.de>
20 - const: rockchip,rk3066-spdif
21 - const: rockchip,rk3228-spdif
22 - const: rockchip,rk3328-spdif
23 - const: rockchip,rk3366-spdif
24 - const: rockchip,rk3368-spdif
[all …]
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| D | rockchip-i2s.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/sound/rockchip-i2s.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 The I2S bus (Inter-IC sound bus) is a serial link for digital
14 - Heiko Stuebner <heiko@sntech.de>
19 - const: rockchip,rk3066-i2s
20 - items:
21 - enum:
22 - rockchip,px30-i2s
[all …]
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| /Linux-v6.1/Documentation/devicetree/bindings/pinctrl/ |
| D | rockchip,pinctrl.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Heiko Stuebner <heiko@sntech.de>
18 Please refer to pinctrl-bindings.txt in this directory for details of the
26 various pad settings such as pull-up, etc.
29 defined as gpio sub-nodes of the pinmux controller.
34 - rockchip,px30-pinctrl
35 - rockchip,rk2928-pinctrl
36 - rockchip,rk3036-pinctrl
[all …]
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| /Linux-v6.1/drivers/phy/rockchip/ |
| D | phy-rockchip-dphy-rx0.c | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
11 * chromeos-4.4 branch.
14 * Jacob Chen <jacob2.chen@rock-chips.com>
15 * Shunqian Zheng <zhengsq@rock-chips.com>
26 #include <linux/phy/phy-mipi-dphy.h>
65 "dphy-ref",
66 "dphy-cfg",
67 "grf",
99 /* below is for rk3399 only */
111 { .offset = _offset, .mask = BIT(_width) - 1, .shift = _shift, }
[all …]
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| /Linux-v6.1/sound/soc/rockchip/ |
| D | rockchip_spdif.c | 1 // SPDX-License-Identifier: GPL-2.0-only
4 * ALSA SoC Audio Layer - Rockchip I2S Controller driver
7 * Author: Jianqun <jay.xu@rock-chips.com>
45 { .compatible = "rockchip,rk3066-spdif",
47 { .compatible = "rockchip,rk3188-spdif",
49 { .compatible = "rockchip,rk3228-spdif",
51 { .compatible = "rockchip,rk3288-spdif",
53 { .compatible = "rockchip,rk3328-spdif",
55 { .compatible = "rockchip,rk3366-spdif",
57 { .compatible = "rockchip,rk3368-spdif",
[all …]
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| /Linux-v6.1/drivers/gpu/drm/rockchip/ |
| D | analogix_dp-rockchip.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * Author: Andy Yan <andy.yan@rock-chips.com>
7 * Yakir Yang <ykk@rock-chips.com>
8 * Jeff Chen <jeff.chen@rock-chips.com>
44 * struct rockchip_dp_chip_data - splite the grf setting of kind of chips
45 * @lcdsel_grf_reg: grf register offset of lcdc select
65 struct regmap *grf; member
88 reset_control_assert(dp->rst); in rockchip_dp_pre_init()
90 reset_control_deassert(dp->rst); in rockchip_dp_pre_init()
100 ret = clk_prepare_enable(dp->pclk); in rockchip_dp_poweron_start()
[all …]
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