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/Linux-v6.1/drivers/video/fbdev/via/
Dvia_clock.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
4 * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
12 #include <linux/via-core.h>
30 return ((pll.divisor - 2) << 16) in k800_encode_pll()
32 | (pll.multiplier - 2); in k800_encode_pll()
44 via_write_reg_mask(VIASR, 0x40, 0x02, 0x02); /* enable reset */ in cle266_set_primary_pll_encoded()
47 via_write_reg_mask(VIASR, 0x40, 0x00, 0x02); /* disable reset */ in cle266_set_primary_pll_encoded()
52 via_write_reg_mask(VIASR, 0x40, 0x02, 0x02); /* enable reset */ in k800_set_primary_pll_encoded()
56 via_write_reg_mask(VIASR, 0x40, 0x00, 0x02); /* disable reset */ in k800_set_primary_pll_encoded()
[all …]
/Linux-v6.1/arch/arm/mach-omap1/
Dreset.c1 // SPDX-License-Identifier: GPL-2.0
3 * OMAP1 reset support
13 /* ARM_SYSST bit shifts related to SoC reset sources */
19 /* Standardized reset source bits (across all OMAP SoCs) */
30 * "Global Software Reset Affects Traffic Controller Frequency". in omap1_restart()
41 * omap1_get_reset_sources - return the source of the SoC's last reset
43 * Returns bits that represent the last reset source for the SoC. The
/Linux-v6.1/Documentation/devicetree/bindings/clock/
Dqcom,qcm2290-dispcc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,qcm2290-dispcc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Display Clock & Reset Controller Binding for qcm2290
10 - Loic Poulain <loic.poulain@linaro.org>
16 See also dt-bindings/clock/qcom,dispcc-qcm2290.h.
20 const: qcom,qcm2290-dispcc
24 - description: Board XO source
25 - description: Board active-only XO source
[all …]
Dqcom,gcc-sm8350.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,gcc-sm8350.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Global Clock & Reset Controller Binding for SM8350
10 - Vinod Koul <vkoul@kernel.org>
17 - dt-bindings/clock/qcom,gcc-sm8350.h
21 const: qcom,gcc-sm8350
25 - description: Board XO source
26 - description: Sleep clock source
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Dqcom,gcc-sc7280.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,gcc-sc7280.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Global Clock & Reset Controller Binding for SC7280
10 - Taniya Das <tdas@codeaurora.org>
17 - dt-bindings/clock/qcom,gcc-sc7280.h
21 const: qcom,gcc-sc7280
25 - description: Board XO source
26 - description: Board active XO source
[all …]
Dqcom,gcc-sm8450.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,gcc-sm8450.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Global Clock & Reset Controller Binding for SM8450
10 - Vinod Koul <vkoul@kernel.org>
17 - dt-bindings/clock/qcom,gcc-sm8450.h
21 const: qcom,gcc-sm8450
25 - description: Board XO source
26 - description: Sleep clock source
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Dqcom,sc7280-camcc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,sc7280-camcc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Camera Clock & Reset Controller Binding for SC7280
10 - Taniya Das <tdas@codeaurora.org>
16 See also dt-bindings/clock/qcom,camcc-sc7280.h
20 const: qcom,sc7280-camcc
24 - description: Board XO source
25 - description: Board XO active source
[all …]
Dqcom,gpucc-sm8350.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,gpucc-sm8350.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Graphics Clock & Reset Controller Binding
10 - Robert Foss <robert.foss@linaro.org>
17 dt-bindings/clock/qcom,gpucc-sm8350.h
22 - qcom,sm8350-gpucc
26 - description: Board XO source
27 - description: GPLL0 main branch source
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Dqcom,sm8450-camcc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,sm8450-camcc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Camera Clock & Reset Controller Binding for SM8450
10 - Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
16 See also include/dt-bindings/clock/qcom,sm8450-camcc.h
20 const: qcom,sm8450-camcc
24 - description: Camera AHB clock from GCC
25 - description: Board XO source
[all …]
Dqcom,gcc-sdm845.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,gcc-sdm845.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Global Clock & Reset Controller Binding
10 - Stephen Boyd <sboyd@kernel.org>
11 - Taniya Das <tdas@codeaurora.org>
18 - dt-bindings/clock/qcom,gcc-sdm845.h
23 - qcom,gcc-sdm670
24 - qcom,gcc-sdm845
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Dqcom,mmcc.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Multimedia Clock & Reset Controller Binding
10 - Jeffrey Hugo <quic_jhugo@quicinc.com>
11 - Taniya Das <tdas@codeaurora.org>
20 - qcom,mmcc-apq8064
21 - qcom,mmcc-apq8084
22 - qcom,mmcc-msm8226
23 - qcom,mmcc-msm8660
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Dqcom,gcc-sdx65.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,gcc-sdx65.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Global Clock & Reset Controller Binding for SDX65
10 - Vamsi krishna Lanka <quic_vamslank@quicinc.com>
17 - dt-bindings/clock/qcom,gcc-sdx65.h
21 const: qcom,gcc-sdx65
25 - description: Board XO source
26 - description: Board active XO source
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Dqcom,gpucc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Graphics Clock & Reset Controller Binding
10 - Taniya Das <tdas@codeaurora.org>
17 dt-bindings/clock/qcom,gpucc-sdm845.h
18 dt-bindings/clock/qcom,gpucc-sc7180.h
19 dt-bindings/clock/qcom,gpucc-sc7280.h
20 dt-bindings/clock/qcom,gpucc-sc8280xp.h
21 dt-bindings/clock/qcom,gpucc-sm6350.h
[all …]
Dqcom,sdm845-dispcc.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,sdm845-dispcc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Display Clock & Reset Controller Binding for SDM845
10 - Taniya Das <tdas@codeaurora.org>
16 See also dt-bindings/clock/qcom,dispcc-sdm845.h.
20 const: qcom,sdm845-dispcc
27 - description: Board XO source
28 - description: GPLL0 source from GCC
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Dsilabs,si5351.txt5 https://www.skyworksinc.com/-/media/Skyworks/SL/documents/public/data-sheets/Si5351-B.pdf
8 clocks. Si5351a also has a reduced pin-count package (MSOP10) where only
15 - compatible: shall be one of the following:
16 "silabs,si5351a" - Si5351a, QFN20 package
17 "silabs,si5351a-msop" - Si5351a, MSOP10 package
18 "silabs,si5351b" - Si5351b, QFN20 package
19 "silabs,si5351c" - Si5351c, QFN20 package
20 - reg: i2c device address, shall be 0x60 or 0x61.
21 - #clock-cells: from common clock binding; shall be set to 1.
22 - clocks: from common clock binding; list of parent clock
[all …]
Dqcom,camcc-sm8250.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,camcc-sm8250.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Camera Clock & Reset Controller Binding for SM8250
10 - Jonathan Marek <jonathan@marek.ca>
16 See also dt-bindings/clock/qcom,camcc-sm8250.h
20 const: qcom,sm8250-camcc
24 - description: Board XO source
25 - description: Sleep clock source
[all …]
Dqcom,msm8998-gpucc.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,msm8998-gpucc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Graphics Clock & Reset Controller Binding for MSM8998
10 - Taniya Das <tdas@codeaurora.org>
16 See also dt-bindings/clock/qcom,gpucc-msm8998.h.
20 const: qcom,msm8998-gpucc
24 - description: Board XO source
25 - description: GPLL0 main branch source (gcc_gpu_gpll0_clk_src)
[all …]
/Linux-v6.1/Documentation/devicetree/bindings/input/
Dnvidia,tegra20-kbc.txt7 - compatible: "nvidia,tegra20-kbc"
8 - reg: Register base address of KBC.
9 - interrupts: Interrupt number for the KBC.
10 - nvidia,kbc-row-pins: The KBC pins which are configured as row. This is an
12 - nvidia,kbc-col-pins: The KBC pins which are configured as column. This is an
14 - linux,keymap: The keymap for keys as described in the binding document
15 devicetree/bindings/input/matrix-keymap.txt.
16 - clocks: Must contain one entry, for the module clock.
17 See ../clocks/clock-bindings.txt for details.
18 - resets: Must contain an entry for each entry in reset-names.
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/Linux-v6.1/Documentation/devicetree/bindings/power/reset/
Dgpio-restart.yaml1 # SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/power/reset/gpio-restart.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: GPIO controlled reset
10 - Sebastian Reichel <sre@kernel.org>
15 This binding supports level and edge triggered reset. At driver load time, the driver will
17 'open-source' is not found, the GPIO line will be driven in the inactive state. Otherwise its
21 is configured as an output, and driven active, triggering a level triggered reset condition.
22 This will also cause an inactive->active edge condition, triggering positive edge triggered
[all …]
/Linux-v6.1/arch/sparc/include/asm/
Dbbc.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * bbc.h: Defines for BootBus Controller found on UltraSPARC-III
12 /* Register sizes are indicated by "B" (Byte, 1-byte),
13 * "H" (Half-word, 2 bytes), "W" (Word, 4 bytes) or
24 #define BBC_PSRC 0x08 /* [W] POR Source */
25 #define BBC_XSRC 0x0c /* [B] XIR Source */
29 #define BBC_ES_DACT 0x14 /* [B] E* De-Assert Change Time */
30 #define BBC_ES_DABT 0x15 /* [B] E* De-Assert Bypass Time */
38 #define BBC_I2C_0_S1 0x2e /* [B] I2C ctrlr-0 reg S1 */
39 #define BBC_I2C_0_S0 0x2f /* [B] I2C ctrlr-0 regs S0,S0',S2,S3*/
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/Linux-v6.1/drivers/reset/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
6 bool "Reset Controller Support"
9 Generic Reset Controller support.
11 This framework is designed to abstract reset handling of devices
12 via GPIOs or SoC-internal reset controller modules.
19 tristate "Altera Arria10 System Resource Reset"
22 This option enables support for the external reset functions for
26 bool "AR71xx Reset Driver" if COMPILE_TEST
29 This enables the ATH79 reset controller driver that supports the
30 AR71xx SoC reset controller.
[all …]
/Linux-v6.1/drivers/net/ethernet/mellanox/mlx4/
Dreset.c8 * COPYING in the main directory of this source tree, or the
11 * Redistribution and use in source and binary forms, with or
15 * - Redistributions of source code must retain the above
19 * - Redistributions in binary form must reproduce the above
44 void __iomem *reset; in mlx4_reset() local
65 * Reset the chip. This is somewhat ugly because we have to in mlx4_reset()
66 * save off the PCI header before reset and then restore it in mlx4_reset()
74 err = -ENOMEM; in mlx4_reset()
79 pcie_cap = pci_pcie_cap(dev->persist->pdev); in mlx4_reset()
84 if (pci_read_config_dword(dev->persist->pdev, i * 4, in mlx4_reset()
[all …]
/Linux-v6.1/Documentation/devicetree/bindings/interrupt-controller/
Dopen-pic.txt13 - compatible: Specifies the compatibility list for the PIC. The type
14 shall be <string> and the value shall include "open-pic".
16 - reg: Specifies the base physical address(s) and size(s) of this
17 PIC's addressable register space. The type shall be <prop-encoded-array>.
19 - interrupt-controller: The presence of this property identifies the node
22 - #interrupt-cells: Specifies the number of cells needed to encode an
23 interrupt source. The type shall be a <u32> and the value shall be 2.
25 - #address-cells: Specifies the number of cells needed to encode an
27 'interrupt-map' nodes do not have to specify a parent unit address.
31 - pic-no-reset: The presence of this property indicates that the PIC
[all …]
/Linux-v6.1/sound/soc/codecs/
Dwm8804.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * wm8804.c -- WM8804 S/PDIF transceiver driver
5 * Copyright 2010-11 Wolfson Microelectronics plc
26 #include <sound/soc-dapm.h>
37 { 3, 0x21 }, /* R3 - PLL1 */
38 { 4, 0xFD }, /* R4 - PLL2 */
39 { 5, 0x36 }, /* R5 - PLL3 */
40 { 6, 0x07 }, /* R6 - PLL4 */
41 { 7, 0x16 }, /* R7 - PLL5 */
42 { 8, 0x18 }, /* R8 - PLL6 */
[all …]
Dcs35l45.c1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
3 // cs35l45.c - CS35L45 ALSA SoC audio driver
5 // Copyright 2019-2022 Cirrus Logic, Inc.
25 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); in cs35l45_global_en_ev()
28 dev_dbg(cs35l45->dev, "%s event : %x\n", __func__, event); in cs35l45_global_en_ev()
32 regmap_write(cs35l45->regmap, CS35L45_GLOBAL_ENABLES, in cs35l45_global_en_ev()
40 regmap_write(cs35l45->regmap, CS35L45_GLOBAL_ENABLES, 0); in cs35l45_global_en_ev()
96 SOC_DAPM_ENUM("ASP_TX1 Source", cs35l45_asp_tx_enums[0]),
97 SOC_DAPM_ENUM("ASP_TX2 Source", cs35l45_asp_tx_enums[1]),
98 SOC_DAPM_ENUM("ASP_TX3 Source", cs35l45_asp_tx_enums[2]),
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