| /Linux-v6.1/Documentation/devicetree/bindings/sound/ |
| D | nvidia,tegra20-ac97.txt | 4 - compatible : "nvidia,tegra20-ac97"
5 - reg : Should contain AC97 controller registers location and length
6 - interrupts : Should contain AC97 interrupt
7 - resets : Must contain an entry for each entry in reset-names.
8 See ../reset/reset.txt for details.
9 - reset-names : Must include the following entries:
10 - ac97
11 - dmas : Must contain an entry for each entry in clock-names.
13 - dma-names : Must include the following entries:
14 - rx
[all …]
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| D | rt5677.txt | 7 - compatible : "realtek,rt5677".
9 - reg : The I2C address of the device.
11 - interrupts : The CODEC's interrupt output.
13 - gpio-controller : Indicates this device is a GPIO controller.
15 - #gpio-cells : Should be two. The first cell is the pin number and the
20 - realtek,pow-ldo2-gpio : The GPIO that controls the CODEC's POW_LDO2 pin.
21 - realtek,reset-gpio : The GPIO that controls the CODEC's RESET pin. Active low.
23 - realtek,in1-differential
24 - realtek,in2-differential
25 - realtek,lout1-differential
[all …]
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| D | cs4271.txt | 7 - compatible: "cirrus,cs4271"
10 Documentation/devicetree/bindings/spi/spi-bus.txt
14 - reg: the i2c address
19 - reset-gpio: a GPIO spec to define which pin is connected to the chip's
20 !RESET pin
21 - cirrus,amuteb-eq-bmutec: When given, the Codec's AMUTEB=BMUTEC flag
23 - cirrus,enable-soft-reset:
24 The CS4271 requires its LRCLK and MCLK to be stable before its RESET
25 line is de-asserted. That also means that clocks cannot be changed
26 without putting the chip back into hardware reset, which also requires
[all …]
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| D | adi,adau1701.txt | 5 - compatible: Should contain "adi,adau1701"
6 - reg: The i2c address. Value depends on the state of ADDR0
11 - reset-gpio: A GPIO spec to define which pin is connected to the
12 chip's !RESET pin. If specified, the driver will
13 assert a hardware reset at probe time.
14 - adi,pll-mode-gpios: An array of two GPIO specs to describe the GPIOs
19 - adi,pin-config: An array of 12 numerical values selecting one of the
23 - avdd-supply: Power supply for AVDD, providing 3.3V
24 - dvdd-supply: Power supply for DVDD, providing 3.3V
32 reset-gpio = <&gpio 23 0>;
[all …]
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| /Linux-v6.1/Documentation/devicetree/bindings/mfd/ |
| D | altera-a10sr.txt | 4 - compatible : "altr,a10sr"
5 - spi-max-frequency : Maximum SPI frequency.
6 - reg : The SPI Chip Select address for the Arria10
8 - interrupts : The interrupt line the device is connected to.
9 - interrupt-controller : Marks the device node as an interrupt controller.
10 - #interrupt-cells : The number of cells to describe an IRQ, should be 2.
13 masks from ../interrupt-controller/interrupts.txt.
15 The A10SR consists of these sub-devices:
18 ------ ----------
19 a10sr_gpio GPIO Controller
[all …]
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| D | delta,tn48m-cpld.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mfd/delta,tn48m-cpld.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Robert Marko <robert.marko@sartura.hr>
19 It is also being used as a GPIO expander and reset controller
20 for the switch MAC-s and other peripherals.
24 const: delta,tn48m-cpld
31 "#address-cells":
34 "#size-cells":
[all …]
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| /Linux-v6.1/Documentation/devicetree/bindings/power/reset/ |
| D | gpio-restart.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/power/reset/gpio-restart.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: GPIO controlled reset
10 - Sebastian Reichel <sre@kernel.org>
13 Drive a GPIO line that can be used to restart the system from a restart handler.
15 This binding supports level and edge triggered reset. At driver load time, the driver will
16 request the given gpio line and install a restart handler. If the optional properties
17 'open-source' is not found, the GPIO line will be driven in the inactive state. Otherwise its
[all …]
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| /Linux-v6.1/drivers/media/pci/cx23885/ |
| D | cx23885-cards.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
14 #include <media/drv-intf/cx25840.h>
19 #include "netup-eeprom.h"
20 #include "netup-init.h"
21 #include "altera-ci.h"
24 #include "cx23888-ir.h"
29 "NetUP Dual DVB-T/C CI card revision");
35 "\t\t\tHVR-1250 (reported safe)\n"
41 /* ------------------------------------------------------------------ */
64 .name = "Hauppauge WinTV-HVR1800lp",
[all …]
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| /Linux-v6.1/arch/arm/boot/dts/ |
| D | armada-385-clearfog-gtr.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
5 * Rabeeh Khoury <rabeeh@solid-run.com>, based on Russell King clearfog work
9 SERDES mapping -
10 0. SATA1 on CON18, or optionally mini PCIe CON3 - PCIe0
12 2. SATA0 on CON17, or optionally mini PCIe CON4 - PCIe1
14 4. mini PCIe CON2 - PCIe2
17 USB 2.0 mapping -
18 0. USB 2.0 - 0 USB pins header CON12
19 1. USB 2.0 - 1 mini PCIe CON2
20 2. USB 2.0 - 2 to USB 3.0 connector (used with SERDES #3)
[all …]
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| D | ste-hrefv60plus.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 2012 ST-Ericsson AB
6 #include "ste-href-ab8500.dtsi"
7 #include "ste-href.dtsi"
10 model = "ST-Ericsson HREF (v60+) platform with Device Tree";
11 compatible = "st-ericsson,hrefv60+", "st-ericsson,u8500";
13 thermal-zones {
14 chassis-thermal {
16 polling-delay = <20000>;
18 polling-delay-passive = <2000>;
[all …]
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| D | ox820.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * ox820.dtsi - Device tree file for Oxford Semiconductor OX820 SoC
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/clock/oxsemi,ox820.h>
10 #include <dt-bindings/reset/oxsemi,ox820.h>
13 #address-cells = <1>;
14 #size-cells = <1>;
18 #address-cells = <1>;
19 #size-cells = <0>;
20 enable-method = "oxsemi,ox820-smp";
[all …]
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| /Linux-v6.1/arch/arm64/boot/dts/hisilicon/ |
| D | hi3798cv200.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
8 #include <dt-bindings/clock/histb-clock.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/phy/phy.h>
12 #include <dt-bindings/reset/ti-syscon.h>
16 interrupt-parent = <&gic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
[all …]
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| /Linux-v6.1/sound/soc/ |
| D | soc-ac97.c | 1 // SPDX-License-Identifier: GPL-2.0+
3 // soc-ac97.c -- ALSA SoC Audio Layer AC97 support
11 // with code, comments and ideas from :-
17 #include <linux/gpio.h>
18 #include <linux/gpio/driver.h>
57 return gpio_priv->component; in gpio_to_component()
63 return -EINVAL; in snd_soc_ac97_gpio_request()
73 dev_dbg(component->dev, "set gpio %d to output\n", offset); in snd_soc_ac97_gpio_direction_in()
85 dev_dbg(component->dev, "get gpio %d : %d\n", offset, in snd_soc_ac97_gpio_get()
97 gpio_priv->gpios_set &= ~(1 << offset); in snd_soc_ac97_gpio_set()
[all …]
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| /Linux-v6.1/Documentation/devicetree/bindings/gpio/ |
| D | gpio-consumer-common.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/gpio/gpio-consumer-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Common GPIO lines
10 - Bartosz Golaszewski <brgl@bgdev.pl>
11 - Linus Walleij <linus.walleij@linaro.org>
14 Pay attention to using proper GPIO flag (e.g. GPIO_ACTIVE_LOW) for the GPIOs
20 enable-gpios:
23 GPIO connected to the enable control pin.
[all …]
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| D | gpio-xra1403.txt | 1 GPIO Driver for XRA1403 16-BIT GPIO Expander With Reset Input from EXAR
3 The XRA1403 is an 16-bit GPIO expander with an SPI interface. Features available:
4 - Individually programmable inputs:
5 - Internal pull-up resistors
6 - Polarity inversion
7 - Individual interrupt enable
8 - Rising edge and/or Falling edge interrupt
9 - Input filter
10 - Individually programmable outputs
11 - Output Level Control
[all …]
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| /Linux-v6.1/drivers/media/pci/cx18/ |
| D | cx18-gpio.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * cx18 gpio functions
5 * Derived from ivtv-gpio.c
11 #include "cx18-driver.h"
12 #include "cx18-io.h"
13 #include "cx18-cards.h"
14 #include "cx18-gpio.h"
17 /********************* GPIO stuffs *********************/
19 /* GPIO registers */
27 * HVR-1600 GPIO pins, courtesy of Hauppauge:
[all …]
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| /Linux-v6.1/arch/arm64/boot/dts/marvell/ |
| D | armada-8040-clearfog-gt-8k.dts | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
9 #include "armada-8040.dtsi"
11 #include <dt-bindings/input/input.h>
12 #include <dt-bindings/gpio/gpio.h>
16 compatible = "solidrun,clearfog-gt-8k", "marvell,armada8040",
17 "marvell,armada-ap806-quad", "marvell,armada-ap806";
20 stdout-path = "serial0:115200n8";
35 compatible = "pwm-fan";
37 cooling-levels = <0 51 102 153 204 255>;
38 #cooling-cells = <2>;
[all …]
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| /Linux-v6.1/Documentation/devicetree/bindings/rtc/ |
| D | moxa,moxart-rtc.txt | 1 MOXA ART real-time clock
5 - compatible : Should be "moxa,moxart-rtc"
6 - gpio-rtc-sclk : RTC sclk gpio, with zero flags
7 - gpio-rtc-data : RTC data gpio, with zero flags
8 - gpio-rtc-reset : RTC reset gpio, with zero flags
13 compatible = "moxa,moxart-rtc";
14 gpio-rtc-sclk = <&gpio 5 0>;
15 gpio-rtc-data = <&gpio 6 0>;
16 gpio-rtc-reset = <&gpio 7 0>;
|
| /Linux-v6.1/arch/arm/mach-pxa/ |
| D | colibri-pcmcia.c | 1 // SPDX-License-Identifier: GPL-2.0-only
13 #include <linux/gpio.h>
15 #include <asm/mach-types.h>
39 RESET = 5, enumerator
42 /* Contents of this array are configured on-the-fly in init function */
43 static struct gpio colibri_pcmcia_gpios[] = {
49 { 0, GPIOF_INIT_HIGH,"PCMCIA Reset" },
61 skt->socket.pci_irq = gpio_to_irq(colibri_pcmcia_gpios[READY].gpio); in colibri_pcmcia_hw_init()
62 skt->stat[SOC_STAT_CD].irq = gpio_to_irq(colibri_pcmcia_gpios[DETECT].gpio); in colibri_pcmcia_hw_init()
63 skt->stat[SOC_STAT_CD].name = "PCMCIA CD"; in colibri_pcmcia_hw_init()
[all …]
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| D | reset.c | 1 // SPDX-License-Identifier: GPL-2.0-only
5 #include <linux/gpio.h>
7 #include <asm/proc-fns.h>
10 #include "regs-ost.h"
11 #include "reset.h"
16 static int reset_gpio = -1;
18 int init_gpio_reset(int gpio, int output, int level) in init_gpio_reset() argument
22 rc = gpio_request(gpio, "reset generator"); in init_gpio_reset()
29 rc = gpio_direction_output(gpio, level); in init_gpio_reset()
31 rc = gpio_direction_input(gpio); in init_gpio_reset()
[all …]
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| D | reset.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
5 #define RESET_STATUS_HARDWARE (1 << 0) /* Hardware Reset */
6 #define RESET_STATUS_WATCHDOG (1 << 1) /* Watchdog Reset */
8 #define RESET_STATUS_GPIO (1 << 3) /* GPIO Reset */
15 * init_gpio_reset() - register GPIO as reset generator
16 * @gpio: gpio nr
17 * @output: set gpio as output instead of input during normal work
20 extern int init_gpio_reset(int gpio, int output, int level);
|
| /Linux-v6.1/Documentation/devicetree/bindings/mmc/ |
| D | mmc-pwrseq-emmc.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mmc/mmc-pwrseq-emmc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Simple eMMC hardware reset provider binding
10 - Ulf Hansson <ulf.hansson@linaro.org>
13 The purpose of this driver is to perform standard eMMC hw reset
19 doesn't have hardware reset logic connected to emmc card and (limited or
25 const: mmc-pwrseq-emmc
27 reset-gpios:
[all …]
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| /Linux-v6.1/Documentation/devicetree/bindings/net/ieee802154/ |
| D | cc2520.txt | 4 - compatible: should be "ti,cc2520"
5 - spi-max-frequency: maximal bus speed (8000000), should be set to 4000000 depends
7 - reg: the chipselect index
8 - pinctrl-0: pin control group to be used for this controller.
9 - pinctrl-names: must contain a "default" entry.
10 - fifo-gpio: GPIO spec for the FIFO pin
11 - fifop-gpio: GPIO spec for the FIFOP pin
12 - sfd-gpio: GPIO spec for the SFD pin
13 - cca-gpio: GPIO spec for the CCA pin
14 - vreg-gpio: GPIO spec for the VREG pin
[all …]
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| D | ca8210.txt | 4 - compatible: Should be "cascoda,ca8210"
5 - reg: Controlling chip select
6 - spi-max-frequency: Maximum clock speed, should be *less than*
8 - spi-cpol: Requires inverted clock polarity
9 - reset-gpio: GPIO attached to reset
10 - irq-gpio: GPIO attached to IRQ
12 - extclock-enable: Include for the ca8210 to route its 16MHz clock
14 - extclock-freq: Frequency in Hz of the external clock
15 - extclock-gpio: GPIO of the ca8210 to output the clock on
21 spi-max-frequency = <3000000>;
[all …]
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| /Linux-v6.1/arch/arm64/boot/dts/microchip/ |
| D | sparx5.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/clock/microchip,sparx5.h>
12 interrupt-parent = <&gic>;
13 #address-cells = <2>;
14 #size-cells = <1>;
23 stdout-path = "serial0:115200n8";
27 #address-cells = <2>;
28 #size-cells = <0>;
[all …]
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