| /Linux-v5.10/Documentation/devicetree/bindings/net/ |
| D | mdio.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andrew Lunn <andrew@lunn.ch>
11 - Florian Fainelli <f.fainelli@gmail.com>
12 - Heiner Kallweit <hkallweit1@gmail.com>
17 bus. These should follow the generic ethernet-phy.yaml document, or
24 "#address-cells":
27 "#size-cells":
30 reset-gpios:
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| D | ethernet-phy.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/net/ethernet-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andrew Lunn <andrew@lunn.ch>
11 - Florian Fainelli <f.fainelli@gmail.com>
12 - Heiner Kallweit <hkallweit1@gmail.com>
14 # The dt-schema tools will generate a select statement first by using
21 pattern: "^ethernet-phy(@[a-f0-9]+)?$"
24 - $nodename
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| D | fsl-fec.txt | 4 - compatible : Should be "fsl,<soc>-fec"
5 - reg : Address and length of the register set for the device
6 - interrupts : Should contain fec interrupt
7 - phy-mode : See ethernet.txt file in the same directory
10 - phy-supply : regulator that powers the Ethernet PHY.
11 - phy-handle : phandle to the PHY device connected to this device.
12 - fixed-link : Assume a fixed link. See fixed-link.txt in the same directory.
13 Use instead of phy-handle.
14 - fsl,num-tx-queues : The property is valid for enet-avb IP, which supports
17 - fsl,num-rx-queues : The property is valid for enet-avb IP, which supports
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| D | hisilicon-femac.txt | 4 - compatible: should contain one of the following version strings:
5 * "hisilicon,hisi-femac-v1"
6 * "hisilicon,hisi-femac-v2"
7 and the soc string "hisilicon,hi3516cv300-femac".
8 - reg: specifies base physical address(s) and size of the device registers.
11 - interrupts: should contain the MAC interrupt.
12 - clocks: A phandle to the MAC main clock.
13 - resets: should contain the phandle to the MAC reset signal(required) and
14 the PHY reset signal(optional).
15 - reset-names: should contain the reset signal name "mac"(required)
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| D | hisilicon-hix5hd2-gmac.txt | 4 - compatible: should contain one of the following SoC strings:
5 * "hisilicon,hix5hd2-gmac"
6 * "hisilicon,hi3798cv200-gmac"
7 * "hisilicon,hi3516a-gmac"
9 * "hisilicon,hisi-gmac-v1"
10 * "hisilicon,hisi-gmac-v2"
13 - reg: specifies base physical address(s) and size of the device registers.
16 - interrupts: should contain the MAC interrupt.
17 - #address-cells: must be <1>.
18 - #size-cells: must be <0>.
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| /Linux-v5.10/Documentation/devicetree/bindings/power/reset/ |
| D | gpio-restart.txt | 4 This binding supports level and edge triggered reset. At driver load
6 handler. If the optional properties 'open-source' is not found, the GPIO line
12 triggering a level triggered reset condition. This will also cause an
13 inactive->active edge condition, triggering positive edge triggered
14 reset. After a delay specified by active-delay, the GPIO is set to
15 inactive, thus causing an active->inactive edge, triggering negative edge
16 triggered reset. After a delay specified by inactive-delay, the GPIO
17 is driven active again. After a delay specified by wait-delay, the
21 - compatible : should be "gpio-restart".
22 - gpios : The GPIO to set high/low, see "gpios property" in
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| /Linux-v5.10/Documentation/devicetree/bindings/display/panel/ |
| D | samsung,s6e8aa0.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andrzej Hajda <a.hajda@samsung.com>
13 - $ref: panel-common.yaml#
20 reset-gpios: true
21 display-timings: true
23 vdd3-supply:
26 vci-supply:
29 power-on-delay:
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| D | samsung,ld9040.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 spi/spi-controller.yaml
14 - Andrzej Hajda <a.hajda@samsung.com>
17 - $ref: panel-common.yaml#
23 display-timings: true
26 reset-gpios: true
28 vdd3-supply:
31 vci-supply:
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| /Linux-v5.10/include/linux/reset/ |
| D | reset-simple.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Simple Reset Controller ops
5 * Based on Allwinner SoCs Reset Controller driver
9 * Maxime Ripard <maxime.ripard@free-electrons.com>
16 #include <linux/reset-controller.h>
20 * struct reset_simple_data - driver data for simple reset controllers
21 * @lock: spinlock to protect registers during read-modify-write cycles
23 * @rcdev: reset controller device base structure
24 * @active_low: if true, bits are cleared to assert the reset. Otherwise, bits
25 * are set to assert the reset. Note that this says nothing about
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| /Linux-v5.10/Documentation/devicetree/bindings/c6x/ |
| D | clocks.txt | 2 -------------------------
4 This is a first-cut support for the SoC clock controllers. This is still
10 - compatible: "ti,c64x+pll"
11 May also have SoC-specific value to support SoC-specific initialization
13 "ti,c6455-pll"
14 "ti,c6457-pll"
15 "ti,c6472-pll"
16 "ti,c6474-pll"
18 - reg: base address and size of register area
19 - clock-frequency: input clock frequency in hz
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| /Linux-v5.10/Documentation/devicetree/bindings/mtd/ |
| D | cadence-quadspi.txt | 4 - compatible : should be one of the following:
5 Generic default - "cdns,qspi-nor".
6 For TI 66AK2G SoC - "ti,k2g-qspi", "cdns,qspi-nor".
7 For TI AM654 SoC - "ti,am654-ospi", "cdns,qspi-nor".
8 - reg : Contains two entries, each of which is a tuple consisting of a
12 - interrupts : Unit interrupt specifier for the controller interrupt.
13 - clocks : phandle to the Quad SPI clock.
14 - cdns,fifo-depth : Size of the data FIFO in words.
15 - cdns,fifo-width : Bus width of the data FIFO in bytes.
16 - cdns,trigger-address : 32-bit indirect AHB trigger address.
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| /Linux-v5.10/Documentation/devicetree/bindings/input/ |
| D | nvidia,tegra20-kbc.txt | 7 - compatible: "nvidia,tegra20-kbc"
8 - reg: Register base address of KBC.
9 - interrupts: Interrupt number for the KBC.
10 - nvidia,kbc-row-pins: The KBC pins which are configured as row. This is an
12 - nvidia,kbc-col-pins: The KBC pins which are configured as column. This is an
14 - linux,keymap: The keymap for keys as described in the binding document
15 devicetree/bindings/input/matrix-keymap.txt.
16 - clocks: Must contain one entry, for the module clock.
17 See ../clocks/clock-bindings.txt for details.
18 - resets: Must contain an entry for each entry in reset-names.
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| /Linux-v5.10/Documentation/devicetree/bindings/mmc/ |
| D | mmc-pwrseq-simple.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mmc/mmc-pwrseq-simple.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ulf Hansson <ulf.hansson@linaro.org>
19 const: mmc-pwrseq-simple
21 reset-gpios:
26 contains a list of GPIO specifiers. The reset GPIOs are asserted
28 They will be de-asserted right after the power has been provided to the
33 description: Handle for the entry in clock-names.
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| /Linux-v5.10/Documentation/devicetree/bindings/spi/ |
| D | nvidia,tegra114-spi.txt | 4 - compatible : For Tegra114, must contain "nvidia,tegra114-spi".
5 Otherwise, must contain '"nvidia,<chip>-spi", "nvidia,tegra114-spi"' where
7 - reg: Should contain SPI registers location and length.
8 - interrupts: Should contain SPI interrupts.
9 - clock-names : Must include the following entries:
10 - spi
11 - resets : Must contain an entry for each entry in reset-names.
12 See ../reset/reset.txt for details.
13 - reset-names : Must include the following entries:
14 - spi
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| /Linux-v5.10/drivers/scsi/qla4xxx/ |
| D | ql4_83xx.c | 1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright (c) 2003-2013 QLogic Corporation
17 return readl((void __iomem *)(ha->nx_pcibase + addr)); in qla4_83xx_rd_reg()
22 writel(val, (void __iomem *)(ha->nx_pcibase + addr)); in qla4_83xx_wr_reg()
30 qla4_83xx_wr_reg(ha, QLA83XX_CRB_WIN_FUNC(ha->func_num), addr); in qla4_83xx_set_win_base()
31 val = qla4_83xx_rd_reg(ha, QLA83XX_CRB_WIN_FUNC(ha->func_num)); in qla4_83xx_set_win_base()
91 __func__, ha->func_num, lock_owner); in qla4_83xx_flash_lock()
98 qla4_83xx_wr_reg(ha, QLA83XX_FLASH_LOCK_ID, ha->func_num); in qla4_83xx_flash_lock()
169 flash_offset = addr & (QLA83XX_FLASH_SECTOR_SIZE - 1); in qla4_83xx_lockless_flash_read_u32()
188 (QLA83XX_FLASH_SECTOR_SIZE - 1)) { in qla4_83xx_lockless_flash_read_u32()
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| /Linux-v5.10/include/linux/dma/ |
| D | xilinx_dma.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
5 * Copyright (C) 2010-2014 Xilinx, Inc. All rights reserved.
11 #include <linux/dma-mapping.h>
15 * struct xilinx_vdma_config - VDMA Configuration structure
16 * @frm_dly: Frame delay
17 * @gen_lock: Whether in gen-lock mode
23 * @delay: Delay counter
24 * @reset: Reset Channel
36 int delay; member
37 int reset; member
|
| /Linux-v5.10/drivers/net/ethernet/qlogic/qlcnic/ |
| D | qlcnic_83xx_init.c | 1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright (c) 2009-2013 QLogic Corporation
11 /* Reset template definitions */
74 u16 delay; member
78 u16 delay;
125 "Need Reset",
136 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE); in qlcnic_83xx_idc_check_driver_presence_reg()
146 cur = adapter->ahw->idc.curr_state; in qlcnic_83xx_idc_log_state_history()
147 prev = adapter->ahw->idc.prev_state; in qlcnic_83xx_idc_log_state_history()
149 dev_info(&adapter->pdev->dev, in qlcnic_83xx_idc_log_state_history()
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| /Linux-v5.10/drivers/input/misc/ |
| D | pmic8xxx-pwrkey.c | 1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
33 /* Regulator control registers for shutdown/reset */
53 /* Buck TEST2 registers for shutdown/reset */
72 * struct pmic8xxx_pwrkey - pmic8xxx pwrkey information
108 enable_irq_wake(pwrkey->key_press_irq); in pmic8xxx_pwrkey_suspend()
118 disable_irq_wake(pwrkey->key_press_irq); in pmic8xxx_pwrkey_resume()
131 bool reset = system_state == SYSTEM_RESTART; in pmic8xxx_pwrkey_shutdown() local
133 if (pwrkey->shutdown_fn) { in pmic8xxx_pwrkey_shutdown()
134 error = pwrkey->shutdown_fn(pwrkey, reset); in pmic8xxx_pwrkey_shutdown()
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| /Linux-v5.10/Documentation/devicetree/bindings/reset/ |
| D | nxp,lpc1850-rgu.txt | 1 NXP LPC1850 Reset Generation Unit (RGU)
4 Please also refer to reset.txt in this directory for common reset
8 - compatible: Should be "nxp,lpc1850-rgu"
9 - reg: register base and length
10 - clocks: phandle and clock specifier to RGU clocks
11 - clock-names: should contain "delay" and "reg"
12 - #reset-cells: should be 1
14 See table below for valid peripheral reset numbers. Numbers not
18 Reset Peripheral
20 12 ARM Cortex-M0 subsystem core (LPC43xx only)
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| /Linux-v5.10/include/linux/usb/ |
| D | isp1362.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 * board initialization code should put one of these into dev->platform_data
15 /* On-chip overcurrent protection */
33 /* Hardware reset set/clear */
34 void (*reset) (struct device *dev, int set); member
37 /* Inter-io delay (ns). The chip is picky about access timings; it
39 * 110ns delay between consecutive accesses to DATA_REG,
40 * 300ns delay between access to ADDR_REG and DATA_REG (registers)
41 * 462ns delay between access to ADDR_REG and DATA_REG (buffer memory)
44 void (*delay) (struct device *dev, unsigned int delay); member
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| /Linux-v5.10/drivers/iio/imu/ |
| D | adis.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * Author: Lars-Peter Clausen <lars@metafoo.de>
9 #include <linux/delay.h>
31 * __adis_write_reg() - write N bytes to register (unlocked version)
45 .tx_buf = adis->tx, in __adis_write_reg()
49 .delay.value = adis->data->write_delay, in __adis_write_reg()
50 .delay.unit = SPI_DELAY_UNIT_USECS, in __adis_write_reg()
51 .cs_change_delay.value = adis->data->cs_change_delay, in __adis_write_reg()
54 .tx_buf = adis->tx + 2, in __adis_write_reg()
58 .delay.value = adis->data->write_delay, in __adis_write_reg()
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| /Linux-v5.10/arch/arm/boot/dts/ |
| D | imx7d-mba7.dts | 1 // SPDX-License-Identifier: GPL-2.0 OR X11
6 * Author: Markus Niebel <Markus.Niebel@tq-group.com>
10 /dts-v1/;
12 #include "imx7d-tqma7.dtsi"
13 #include "imx7-mba7.dtsi"
17 compatible = "tq,imx7d-mba7", "fsl,imx7d";
21 pinctrl-names = "default";
22 pinctrl-0 = <&pinctrl_enet2>;
23 phy-mode = "rgmii-id";
24 phy-reset-gpios = <&gpio2 28 GPIO_ACTIVE_LOW>;
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| D | tegra124.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra124-car.h>
3 #include <dt-bindings/gpio/tegra-gpio.h>
4 #include <dt-bindings/memory/tegra124-mc.h>
5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/reset/tegra124-car.h>
8 #include <dt-bindings/thermal/tegra124-soctherm.h>
9 #include <dt-bindings/soc/tegra-pmc.h>
13 interrupt-parent = <&lic>;
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| /Linux-v5.10/drivers/mmc/host/ |
| D | sdhci-bcm-kona.c | 16 #include <linux/delay.h>
25 #include <linux/mmc/slot-gpio.h>
27 #include "sdhci-pltfm.h"
63 /* This timeout should be sufficent for core to reset */ in sdhci_bcm_kona_sd_reset()
66 /* reset the host using the top level reset */ in sdhci_bcm_kona_sd_reset()
73 pr_err("Error: sd host is stuck in reset!!!\n"); in sdhci_bcm_kona_sd_reset()
74 return -EFAULT; in sdhci_bcm_kona_sd_reset()
78 /* bring the host out of reset */ in sdhci_bcm_kona_sd_reset()
83 * Back-to-Back register write needs a delay of 1ms at bootup (min 10uS) in sdhci_bcm_kona_sd_reset()
84 * Back-to-Back writes to same register needs delay when SD bus clock in sdhci_bcm_kona_sd_reset()
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| /Linux-v5.10/drivers/gpu/drm/i915/ |
| D | Kconfig.profile | 14 int "Runtime autosuspend delay for userspace GGTT mmaps (ms)"
21 that complements the runtime-pm autosuspend and provides a lower
22 floor on the autosuspend delay.
24 May be 0 to disable the extra delay and solely use the device level
25 runtime pm autosuspend delay tunable.
32 check the health of the GPU and undertake regular house-keeping of
48 expires, the HW will be reset to allow the more important context
66 take a non-negligible time to setup, we do a short spin first to
78 int "How long to wait for an engine to quiesce gracefully before reset (ms)"
84 damage as the system is reset in order to recover. The corollary is
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