| /Linux-v5.10/drivers/reset/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
6 bool "Reset Controller Support"
9 Generic Reset Controller support.
11 This framework is designed to abstract reset handling of devices
12 via GPIOs or SoC-internal reset controller modules.
19 tristate "Altera Arria10 System Resource Reset"
22 This option enables support for the external reset functions for
26 bool "AR71xx Reset Driver" if COMPILE_TEST
29 This enables the ATH79 reset controller driver that supports the
30 AR71xx SoC reset controller.
[all …]
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| D | reset-scmi.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * ARM System Control and Management Interface (ARM SCMI) reset driver
11 #include <linux/reset-controller.h>
15 * struct scmi_reset_data - reset controller information structure
16 * @rcdev: reset controller entity
17 * @handle: ARM SCMI handle used for communication with system controller
25 #define to_scmi_handle(p) (to_scmi_reset_data(p)->handle)
28 * scmi_reset_assert() - assert device reset
29 * @rcdev: reset controller entity
30 * @id: ID of the reset to be asserted
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| D | core.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Reset Controller framework
15 #include <linux/reset.h>
16 #include <linux/reset-controller.h>
26 * struct reset_control - a reset control
27 * @rcdev: a pointer to the reset controller device
28 * this reset control belongs to
29 * @list: list entry for the rcdev's reset controller list
30 * @id: ID of the reset controller in the reset
31 * controller device
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| D | reset-ti-sci.c | 2 * Texas Instrument's System Control Interface (TI-SCI) reset driver
4 * Copyright (C) 2015-2017 Texas Instruments Incorporated - https://www.ti.com/
22 #include <linux/reset-controller.h>
26 * struct ti_sci_reset_control - reset control structure
27 * @dev_id: SoC-specific device identifier
28 * @reset_mask: reset mask to use for toggling reset
29 * @lock: synchronize reset_mask read-modify-writes
38 * struct ti_sci_reset_data - reset controller information structure
39 * @rcdev: reset controller entity
40 * @dev: reset controller device pointer
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| /Linux-v5.10/Documentation/devicetree/bindings/reset/ |
| D | ti,sci-reset.txt | 1 Texas Instruments System Control Interface (TI-SCI) Reset Controller
4 Some TI SoCs contain a system controller (like the Power Management Micro
5 Controller (PMMC) on Keystone 66AK2G SoC) that are responsible for controlling
7 between the host processor running an OS and the system controller happens
8 through a protocol called TI System Control Interface (TI-SCI protocol).
12 TI-SCI Reset Controller Node
14 This reset controller node uses the TI SCI protocol to perform the reset
16 node of the associated TI-SCI system controller node.
19 --------------------
20 - compatible : Should be "ti,sci-reset"
[all …]
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| D | ti-syscon-reset.txt | 1 TI SysCon Reset Controller
4 Almost all SoCs have hardware modules that require reset control in addition
5 to clock and power control for their functionality. The reset control is
6 typically provided by means of memory-mapped I/O registers. These registers are
12 A SysCon Reset Controller node defines a device that uses a syscon node
13 and provides reset management functionality for various hardware modules
16 SysCon Reset Controller Node
18 Each of the reset provider/controller nodes should be a child of a syscon
22 --------------------
23 - compatible : Should be,
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| D | amlogic,meson-reset.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: "http://devicetree.org/schemas/reset/amlogic,meson-reset.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
8 title: Amlogic Meson SoC Reset Controller
11 - Neil Armstrong <narmstrong@baylibre.com>
16 - amlogic,meson8b-reset # Reset Controller on Meson8b and compatible SoCs
17 - amlogic,meson-gxbb-reset # Reset Controller on GXBB and compatible SoCs
18 - amlogic,meson-axg-reset # Reset Controller on AXG and compatible SoCs
19 - amlogic,meson-a1-reset # Reset Controller on A1 and compatible SoCs
[all …]
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| D | hisilicon,hi6220-reset.txt | 1 Hisilicon System Reset Controller
4 Please also refer to reset.txt in this directory for common reset
5 controller binding usage.
7 The reset controller registers are part of the system-ctl block on
11 - compatible: should be one of the following:
12 - "hisilicon,hi6220-sysctrl", "syscon" : For peripheral reset controller.
13 - "hisilicon,hi6220-mediactrl", "syscon" : For media reset controller.
14 - "hisilicon,hi6220-aoctrl", "syscon" : For ao reset controller.
15 - reg: should be register base and length as documented in the
17 - #reset-cells: 1, see below
[all …]
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| D | snps,dw-reset.txt | 1 Synopsys DesignWare Reset controller
4 Please also refer to reset.txt in this directory for common reset
5 controller binding usage.
9 - compatible: should be one of the following.
10 "snps,dw-high-reset" - for active high configuration
11 "snps,dw-low-reset" - for active low configuration
13 - reg: physical base address of the controller and length of memory mapped
16 - #reset-cells: must be 1.
20 dw_rst_1: reset-controller@0000 {
21 compatible = "snps,dw-high-reset";
[all …]
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| D | brcm,brcmstb-reset.txt | 1 Broadcom STB SW_INIT-style reset controller
4 Broadcom STB SoCs have a SW_INIT-style reset controller with separate
6 reset lines.
8 Please also refer to reset.txt in this directory for common reset
9 controller binding usage.
12 - compatible: should be brcm,brcmstb-reset
13 - reg: register base and length
14 - #reset-cells: must be set to 1
18 reset: reset-controller@8404318 {
19 compatible = "brcm,brcmstb-reset";
[all …]
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| D | st,sti-powerdown.txt | 1 STMicroelectronics STi family Sysconfig Peripheral Powerdown Reset Controller
4 This binding describes a reset controller device that is used to enable and
5 disable on-chip peripheral controllers such as USB and SATA, using
7 registers. These have been grouped together into a single reset controller
15 Please refer to reset.txt in this directory for common reset
16 controller binding usage.
19 - compatible: Should be "st,stih407-powerdown"
20 - #reset-cells: 1, see below
24 powerdown: powerdown-controller {
25 compatible = "st,stih407-powerdown";
[all …]
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| D | bitmain,bm1880-reset.txt | 1 Bitmain BM1880 SoC Reset Controller
4 Please also refer to reset.txt in this directory for common reset
5 controller binding usage.
8 - compatible: Should be "bitmain,bm1880-reset"
9 - reg: Offset and length of reset controller space in SCTRL.
10 - #reset-cells: Must be 1.
14 rst: reset-controller@c00 {
15 compatible = "bitmain,bm1880-reset";
17 #reset-cells = <1>;
|
| D | berlin,reset.txt | 1 Marvell Berlin reset controller
4 Please also refer to reset.txt in this directory for common reset
5 controller binding usage.
7 The reset controller node must be a sub-node of the chip controller
11 - compatible: should be "marvell,berlin2-reset"
12 - #reset-cells: must be set to 2
16 chip_rst: reset {
17 compatible = "marvell,berlin2-reset";
18 #reset-cells = <2>;
|
| D | fsl,imx7-src.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/reset/fsl,imx7-src.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale i.MX7 System Reset Controller
10 - Andrey Smirnov <andrew.smirnov@gmail.com>
13 The system reset controller can be used to reset various set of
14 peripherals. Device nodes that need access to reset lines should
15 specify them as a reset phandle in their corresponding node as
16 specified in reset.txt.
[all …]
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| D | zte,zx2967-reset.txt | 1 ZTE zx2967 SoCs Reset Controller
4 Please also refer to reset.txt in this directory for common reset
5 controller binding usage.
8 - compatible: should be one of the following.
9 * zte,zx296718-reset
10 - reg: physical base address of the controller and length of memory mapped
12 - #reset-cells: must be 1.
16 reset: reset-controller@1461060 {
17 compatible = "zte,zx296718-reset";
19 #reset-cells = <1>;
|
| /Linux-v5.10/include/linux/ |
| D | reset.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
79 return optional ? 0 : -ENOTSUPP; in __device_reset()
87 return optional ? NULL : ERR_PTR(-ENOTSUPP); in __of_reset_control_get()
95 return optional ? NULL : ERR_PTR(-ENOTSUPP); in __reset_control_get()
103 return optional ? NULL : ERR_PTR(-ENOTSUPP); in __devm_reset_control_get()
109 return optional ? NULL : ERR_PTR(-ENOTSUPP); in devm_reset_control_array_get()
116 return optional ? NULL : ERR_PTR(-ENOTSUPP); in of_reset_control_array_get()
121 return -ENOENT; in reset_control_get_count()
137 * reset_control_get_exclusive - Lookup and obtain an exclusive reference
138 * to a reset controller.
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| D | reset-controller.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
10 * struct reset_control_ops - reset controller driver callbacks
12 * @reset: for self-deasserting resets, does all necessary
13 * things to reset the device
14 * @assert: manually assert the reset line, if supported
15 * @deassert: manually deassert the reset line, if supported
16 * @status: return the status of the reset line, if supported
19 int (*reset)(struct reset_controller_dev *rcdev, unsigned long id); member
30 * struct reset_control_lookup - represents a single lookup entry
32 * @list: internal list of all reset lookup entries
[all …]
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| /Linux-v5.10/Documentation/devicetree/bindings/display/tegra/ |
| D | nvidia,tegra20-host1x.txt | 4 - compatible: "nvidia,tegra<chip>-host1x"
5 - reg: Physical base address and length of the controller's registers.
6 For pre-Tegra186, one entry describing the whole register area.
7 For Tegra186, one entry for each entry in reg-names:
8 "vm" - VM region assigned to Linux
9 "hypervisor" - Hypervisor region (only if Linux acts as hypervisor)
10 - interrupts: The interrupt outputs from the controller.
11 - #address-cells: The number of cells used to represent physical base addresses
13 - #size-cells: The number of cells used to represent the size of an address
15 - ranges: The mapping of the host1x address space to the CPU address space.
[all …]
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| /Linux-v5.10/drivers/reset/sti/ |
| D | reset-syscfg.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
11 #include <linux/reset-controller.h>
14 * Reset channel description for a system configuration register based
15 * reset controller.
19 * @reset: Regmap field description of the channel's reset bit.
24 struct reg_field reset; member
30 .reset = REG_FIELD(_rr, _rb, _rb), \
35 .reset = REG_FIELD(_rr, _rb, _rb), }
38 * Description of a system configuration register based reset controller.
40 * @wait_for_ack: The controller will wait for reset assert and de-assert to
[all …]
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| /Linux-v5.10/Documentation/devicetree/bindings/mfd/ |
| D | altera-a10sr.txt | 4 - compatible : "altr,a10sr"
5 - spi-max-frequency : Maximum SPI frequency.
6 - reg : The SPI Chip Select address for the Arria10
8 - interrupts : The interrupt line the device is connected to.
9 - interrupt-controller : Marks the device node as an interrupt controller.
10 - #interrupt-cells : The number of cells to describe an IRQ, should be 2.
13 masks from ../interrupt-controller/interrupts.txt.
15 The A10SR consists of these sub-devices:
18 ------ ----------
19 a10sr_gpio GPIO Controller
[all …]
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| D | aspeed-lpc.txt | 2 Device tree bindings for the Aspeed Low Pin Count (LPC) Bus Controller
5 The LPC bus is a means to bridge a host CPU to a number of low-bandwidth
7 primary use case of the Aspeed LPC controller is as a slave on the bus
8 (typically in a Baseboard Management Controller SoC), but under certain
11 The LPC controller is represented as a multi-function device to account for the
14 "basically compatible with the [LPC registers from the] popular BMC controller
17 here labeled the "host" portion of the controller, includes, but is not limited
20 * An IPMI Block Transfer[2] Controller
22 * An LPC Host Controller: Manages LPC functions such as host vs slave mode, the
24 APB-to-LPC bridging amonst other functions.
[all …]
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| /Linux-v5.10/include/linux/reset/ |
| D | reset-simple.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Simple Reset Controller ops
5 * Based on Allwinner SoCs Reset Controller driver
9 * Maxime Ripard <maxime.ripard@free-electrons.com>
16 #include <linux/reset-controller.h>
20 * struct reset_simple_data - driver data for simple reset controllers
21 * @lock: spinlock to protect registers during read-modify-write cycles
23 * @rcdev: reset controller device base structure
24 * @active_low: if true, bits are cleared to assert the reset. Otherwise, bits
25 * are set to assert the reset. Note that this says nothing about
[all …]
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| /Linux-v5.10/arch/arm64/boot/dts/amlogic/ |
| D | meson-g12.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include "meson-g12-common.dtsi"
8 #include <dt-bindings/clock/axg-audio-clkc.h>
9 #include <dt-bindings/power/meson-g12a-power.h>
10 #include <dt-bindings/reset/amlogic,meson-axg-audio-arb.h>
11 #include <dt-bindings/reset/amlogic,meson-g12a-audio-reset.h>
14 tdmif_a: audio-controller-0 {
15 compatible = "amlogic,axg-tdm-iface";
16 #sound-dai-cells = <0>;
17 sound-name-prefix = "TDM_A";
[all …]
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| /Linux-v5.10/arch/arm/mach-tegra/ |
| D | platsmp.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * linux/arch/arm/mach-tegra/platsmp.c
26 #include <asm/mach-types.h>
32 #include "reset.h"
47 * Force the CPU into reset. The CPU must remain in reset when in tegra20_boot_secondary()
48 * the flow controller state is cleared (which will cause the in tegra20_boot_secondary()
49 * flow controller to stop driving reset if the CPU has been in tegra20_boot_secondary()
50 * power-gated via the flow controller). This will have no in tegra20_boot_secondary()
52 * in reset. in tegra20_boot_secondary()
57 * Unhalt the CPU. If the flow controller was used to in tegra20_boot_secondary()
[all …]
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| /Linux-v5.10/Documentation/devicetree/bindings/power/reset/ |
| D | keystone-reset.txt | 1 * Device tree bindings for Texas Instruments keystone reset
3 This node is intended to allow SoC reset in case of software reset
6 The Keystone SoCs can contain up to 4 watchdog timers to reset
7 SoC. Each watchdog timer event input is connected to the Reset Mux
8 block. The Reset Mux block can be configured to cause reset or not.
10 Additionally soft or hard reset can be configured.
14 - compatible: ti,keystone-reset
16 - ti,syscon-pll: phandle/offset pair. The phandle to syscon used to
17 access pll controller registers and the offset to use
18 reset control registers.
[all …]
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