/Linux-v5.4/Documentation/devicetree/bindings/net/ |
D | ethernet-phy.yaml | 1 # SPDX-License-Identifier: GPL-2.0 3 --- 4 $id: http://devicetree.org/schemas/net/ethernet-phy.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Andrew Lunn <andrew@lunn.ch> 11 - Florian Fainelli <f.fainelli@gmail.com> 12 - Heiner Kallweit <hkallweit1@gmail.com> 14 # The dt-schema tools will generate a select statement first by using 21 pattern: "^ethernet-phy(@[a-f0-9]+)?$" 24 - $nodename [all …]
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/Linux-v5.4/drivers/reset/ |
D | reset-imx7.c | 1 // SPDX-License-Identifier: GPL-2.0-only 5 * i.MX7 System Reset Controller (SRC) driver 14 #include <linux/reset-controller.h> 16 #include <dt-bindings/reset/imx7-reset.h> 17 #include <dt-bindings/reset/imx8mq-reset.h> 50 const struct imx7_src_signal *signal = &imx7src->signals[id]; in imx7_reset_update() 52 return regmap_update_bits(imx7src->regmap, in imx7_reset_update() 53 signal->offset, signal->bit, value); in imx7_reset_update() 91 unsigned long id, bool assert) in imx7_reset_set() argument 94 const unsigned int bit = imx7src->signals[id].bit; in imx7_reset_set() [all …]
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D | reset-brcmstb.c | 1 // SPDX-License-Identifier: GPL-2.0 3 * Broadcom STB generic reset controller for SW_INIT style reset controller 14 #include <linux/reset-controller.h> 46 writel_relaxed(SW_INIT_BIT(id), priv->base + off + SW_INIT_SET); in brcmstb_reset_assert() 57 writel_relaxed(SW_INIT_BIT(id), priv->base + off + SW_INIT_CLEAR); in brcmstb_reset_deassert() 58 /* Maximum reset delay after de-asserting a line and seeing block in brcmstb_reset_deassert() 59 * operation is typically 14us for the worst case, build some slack in brcmstb_reset_deassert() 73 return readl_relaxed(priv->base + off + SW_INIT_STATUS) & in brcmstb_reset_status() 78 .assert = brcmstb_reset_assert, 85 struct device *kdev = &pdev->dev; in brcmstb_reset_probe() [all …]
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/Linux-v5.4/Documentation/devicetree/bindings/thermal/ |
D | nvidia,tegra124-soctherm.txt | 4 or interrupt-based thermal monitoring, CPU and GPU throttling based 10 - compatible : For Tegra124, must contain "nvidia,tegra124-soctherm". 11 For Tegra132, must contain "nvidia,tegra132-soctherm". 12 For Tegra210, must contain "nvidia,tegra210-soctherm". 13 - reg : Should contain at least 2 entries for each entry in reg-names: 14 - SOCTHERM register set 15 - Tegra CAR register set: Required for Tegra124 and Tegra210. 16 - CCROC register set: Required for Tegra132. 17 - reg-names : Should contain at least 2 entries: 18 - soctherm-reg [all …]
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/Linux-v5.4/arch/arm64/boot/dts/amlogic/ |
D | meson-gxm-q200.dts | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 7 /dts-v1/; 9 #include <dt-bindings/input/input.h> 11 #include "meson-gxm.dtsi" 12 #include "meson-gx-p23x-q20x.dtsi" 15 compatible = "amlogic,q200", "amlogic,s912", "amlogic,meson-gxm"; 18 adc-keys { 19 compatible = "adc-keys"; 20 io-channels = <&saradc 0>; 21 io-channel-names = "buttons"; [all …]
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D | meson-gxl-s905d-p230.dts | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 7 /dts-v1/; 9 #include <dt-bindings/input/input.h> 11 #include "meson-gxl-s905d.dtsi" 12 #include "meson-gx-p23x-q20x.dtsi" 15 compatible = "amlogic,p230", "amlogic,s905d", "amlogic,meson-gxl"; 18 adc-keys { 19 compatible = "adc-keys"; 20 io-channels = <&saradc 0>; 21 io-channel-names = "buttons"; [all …]
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D | meson-gxbb-p200.dts | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 8 /dts-v1/; 10 #include "meson-gxbb-p20x.dtsi" 11 #include <dt-bindings/input/input.h> 14 compatible = "amlogic,p200", "amlogic,meson-gxbb"; 17 avdd18_usb_adc: regulator-avdd18_usb_adc { 18 compatible = "regulator-fixed"; 19 regulator-name = "AVDD18_USB_ADC"; 20 regulator-min-microvolt = <1800000>; 21 regulator-max-microvolt = <1800000>; [all …]
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D | meson-gxm-nexbox-a1.dts | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 10 /dts-v1/; 12 #include "meson-gxm.dtsi" 15 compatible = "nexbox,a1", "amlogic,s912", "amlogic,meson-gxm"; 24 stdout-path = "serial0:115200n8"; 32 vddio_boot: regulator-vddio-boot { 33 compatible = "regulator-fixed"; 34 regulator-name = "VDDIO_BOOT"; 35 regulator-min-microvolt = <1800000>; 36 regulator-max-microvolt = <1800000>; [all …]
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D | meson-gxm-rbox-pro.dts | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 3 * Copyright (c) 2016-2017 Andreas Färber 5 * Based on nexbox-a1: 14 /dts-v1/; 16 #include "meson-gxm.dtsi" 19 compatible = "kingnovel,r-box-pro", "amlogic,s912", "amlogic,meson-gxm"; 20 model = "R-Box Pro"; 28 stdout-path = "serial0:115200n8"; 37 compatible = "gpio-leds"; 40 label = "rbox-pro:blue:on"; [all …]
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D | meson-gxbb-nexbox-a95x.dts | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 8 /dts-v1/; 10 #include "meson-gxbb.dtsi" 11 #include <dt-bindings/gpio/gpio.h> 12 #include <dt-bindings/input/input.h> 15 compatible = "nexbox,a95x", "amlogic,meson-gxbb"; 24 stdout-path = "serial0:115200n8"; 33 compatible = "gpio-leds"; 35 label = "a95x:system-status"; 37 linux,default-trigger = "heartbeat"; [all …]
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D | meson-gxbb-wetek.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 8 #include "meson-gxbb.dtsi" 17 stdout-path = "serial0:115200n8"; 26 compatible = "gpio-leds"; 29 label = "wetek-play:system-status"; 31 default-state = "on"; 32 panic-indicator; 36 usb_pwr: regulator-usb-pwrs { 37 compatible = "regulator-fixed"; 39 regulator-name = "USB_PWR"; [all …]
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D | meson-gxbb-vega-s95.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 6 #include "meson-gxbb.dtsi" 9 compatible = "tronsmart,vega-s95", "amlogic,meson-gxbb"; 17 stdout-path = "serial0:115200n8"; 21 compatible = "gpio-leds"; 24 label = "vega-s95:blue:on"; 26 default-state = "on"; 27 panic-indicator; 31 usb_pwr: regulator-usb-pwrs { 32 compatible = "regulator-fixed"; [all …]
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D | meson-gxbb-nanopi-k2.dts | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 6 /dts-v1/; 8 #include "meson-gxbb.dtsi" 9 #include <dt-bindings/gpio/gpio.h> 12 compatible = "friendlyarm,nanopi-k2", "amlogic,meson-gxbb"; 21 stdout-path = "serial0:115200n8"; 30 compatible = "gpio-leds"; 33 label = "nanopi-k2:blue:stat"; 35 default-state = "on"; 36 panic-indicator; [all …]
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/Linux-v5.4/drivers/gpu/drm/msm/hdmi/ |
D | hdmi_pll_8960.c | 1 // SPDX-License-Identifier: GPL-2.0-only 8 #include <linux/clk-provider.h> 27 * configuration into common-clock-framework. 239 msm_writel(data, pll->mmio + reg); in pll_write() 244 return msm_readl(pll->mmio + reg); in pll_read() 249 return platform_get_drvdata(pll->pdev); in pll_get_phy() 261 /* Assert PLL S/W reset */ in hdmi_pll_enable() 266 /* Wait for a short time before de-asserting in hdmi_pll_enable() 269 * to assert and de-assert. in hdmi_pll_enable() 273 /* De-assert PLL S/W reset */ in hdmi_pll_enable() [all …]
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/Linux-v5.4/drivers/clk/qcom/ |
D | clk-pll.c | 1 // SPDX-License-Identifier: GPL-2.0-only 12 #include <linux/clk-provider.h> 17 #include "clk-pll.h" 31 ret = regmap_read(pll->clkr.regmap, pll->mode_reg, &val); in clk_pll_enable() 40 ret = regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_BYPASSNL, in clk_pll_enable() 46 * H/W requires a 5us delay between disabling the bypass and in clk_pll_enable() 47 * de-asserting the reset. Delay 10us just to be safe. in clk_pll_enable() 51 /* De-assert active-low PLL reset. */ in clk_pll_enable() 52 ret = regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_RESET_N, in clk_pll_enable() 61 return regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_OUTCTRL, in clk_pll_enable() [all …]
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D | clk-hfpll.c | 1 // SPDX-License-Identifier: GPL-2.0 9 #include <linux/clk-provider.h> 12 #include "clk-regmap.h" 13 #include "clk-hfpll.h" 23 struct hfpll_data const *hd = h->d; in __clk_hfpll_init_once() 24 struct regmap *regmap = h->clkr.regmap; in __clk_hfpll_init_once() 26 if (likely(h->init_done)) in __clk_hfpll_init_once() 30 if (hd->config_val) in __clk_hfpll_init_once() 31 regmap_write(regmap, hd->config_reg, hd->config_val); in __clk_hfpll_init_once() 32 regmap_write(regmap, hd->m_reg, 0); in __clk_hfpll_init_once() [all …]
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/Linux-v5.4/drivers/staging/fieldbus/anybuss/ |
D | arcx-anybus.c | 1 // SPDX-License-Identifier: GPL-2.0 3 * Arcx Anybus-S Controller driver 23 /* move to <linux/anybuss-controller.h> when taking this out of staging */ 24 #include "anybuss-controller.h" 50 static void do_reset(struct controller_priv *cd, u8 rst_bit, bool reset) in do_reset() argument 52 mutex_lock(&cd->ctrl_lock); in do_reset() 54 * CPLD_CONTROL is write-only, so cache its value in in do_reset() 55 * cd->control_reg in do_reset() 57 if (reset) in do_reset() 58 cd->control_reg &= ~rst_bit; in do_reset() [all …]
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/Linux-v5.4/drivers/remoteproc/ |
D | qcom_q6v5_wcss.c | 1 // SPDX-License-Identifier: GPL-2.0 3 * Copyright (C) 2016-2018 Linaro Ltd. 5 * Copyright (c) 2012-2018, The Linux Foundation. All rights reserved. 14 #include <linux/reset.h> 102 /* Assert resets, stop core */ in q6v5_wcss_reset() 103 val = readl(wcss->reg_base + Q6SS_RESET_REG); in q6v5_wcss_reset() 105 writel(val, wcss->reg_base + Q6SS_RESET_REG); in q6v5_wcss_reset() 108 val = readl(wcss->reg_base + Q6SS_XO_CBCR); in q6v5_wcss_reset() 110 writel(val, wcss->reg_base + Q6SS_XO_CBCR); in q6v5_wcss_reset() 113 ret = readl_poll_timeout(wcss->reg_base + Q6SS_XO_CBCR, in q6v5_wcss_reset() [all …]
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/Linux-v5.4/arch/arm/boot/dts/ |
D | meson8b-mxq.dts | 1 // SPDX-License-Identifier: GPL-2.0 OR MIT 7 /dts-v1/; 9 #include <dt-bindings/gpio/gpio.h> 22 stdout-path = "serial0:115200n8"; 30 iio-hwmon { 31 compatible = "iio-hwmon"; 32 io-channels = <&saradc 8>; 35 vcck: regulator-vcck { 36 compatible = "pwm-regulator"; 38 regulator-name = "VCCK"; [all …]
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D | sun7i-a20-hummingbird.dts | 6 * This file is dual-licensed: you can use it either under the terms 45 /dts-v1/; 46 #include "sun7i-a20.dtsi" 47 #include "sunxi-common-regulators.dtsi" 49 #include <dt-bindings/gpio/gpio.h> 50 #include <dt-bindings/interrupt-controller/irq.h> 54 compatible = "merrii,a20-hummingbird", "allwinner,sun7i-a20"; 65 stdout-path = "serial0:115200n8"; 69 compatible = "regulator-fixed"; 70 regulator-name = "mmc3_vdd"; [all …]
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D | meson8m2-mxiii-plus.dts | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 3 * Copyright (c) 2018 Oleg Ivanov <balbes-150@yandex.ru> 7 /dts-v1/; 11 #include <dt-bindings/gpio/gpio.h> 12 #include <dt-bindings/input/input.h> 16 compatible = "tronsmart,mxiii-plus", "amlogic,meson8m2"; 27 stdout-path = "serial0:115200n8"; 35 adc-keys { 36 compatible = "adc-keys"; 37 io-channels = <&saradc 0>; [all …]
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/Linux-v5.4/drivers/fpga/ |
D | ice40-spi.c | 1 // SPDX-License-Identifier: GPL-2.0-only 11 #include <linux/fpga/fpga-mgr.h> 21 #define ICE40_SPI_RESET_DELAY 1 /* us (>200ns) */ 22 #define ICE40_SPI_HOUSEKEEPING_DELAY 1200 /* us */ 28 struct gpio_desc *reset; member 34 struct ice40_fpga_priv *priv = mgr->priv; in ice40_fpga_ops_state() 36 return gpiod_get_value(priv->cdone) ? FPGA_MGR_STATE_OPERATING : in ice40_fpga_ops_state() 44 struct ice40_fpga_priv *priv = mgr->priv; in ice40_fpga_ops_write_init() 45 struct spi_device *dev = priv->dev; in ice40_fpga_ops_write_init() 56 if ((info->flags & FPGA_MGR_PARTIAL_RECONFIG)) { in ice40_fpga_ops_write_init() [all …]
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/Linux-v5.4/sound/arm/ |
D | pxa2xx-ac97-lib.c | 1 // SPDX-License-Identifier: GPL-2.0-only 3 * Based on sound/arm/pxa2xx-ac97.c and sound/soc/pxa/pxa2xx-ac97.c 21 #include <sound/pxa2xx-lib.h> 24 #include <mach/regs-ac97.h> 48 int val = -ENODEV; in pxa2xx_ac97_read() 52 return -ENODEV; in pxa2xx_ac97_read() 73 val = -ETIMEDOUT; in pxa2xx_ac97_read() 110 ret = -EIO; in pxa2xx_ac97_write() 129 GCR &= ~GCR_COLD_RST; /* then assert nCRST */ in pxa_ac97_cold_pxa25x() 142 /* warm reset broken on Bulverde, so manually keep AC97 reset high */ in pxa_ac97_warm_pxa27x() [all …]
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/Linux-v5.4/arch/arm/mach-sunxi/ |
D | mc_smp.c | 1 // SPDX-License-Identifier: GPL-2.0 3 * Copyright (c) 2018 Chen-Yu Tsai 5 * Chen-Yu Tsai <wens@csie.org> 7 * arch/arm/mach-sunxi/mc_smp.c 9 * Based on Allwinner code, arch/arm/mach-exynos/mcpm-exynos.c, and 10 * arch/arm/mach-hisi/platmcpm.c 14 #include <linux/arm-cci.h> 19 #include <linux/irqchip/arm-gic.h> 71 /* R_CPUCFG registers, specific to sun8i-a83t */ 111 is_compatible = of_device_is_compatible(node, "arm,cortex-a15"); in sunxi_core_is_cortex_a15() [all …]
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/Linux-v5.4/fs/xfs/libxfs/ |
D | xfs_defer.c | 1 // SPDX-License-Identifier: GPL-2.0+ 32 * necessary to perform complex remapping multi-transactions to comply 34 * refcount update operation (an operation on an n-block extent can 37 * requires us to log "intent" items in case log recovery needs to 48 * start, we define "rolling a deferred-op transaction" as follows: 51 * - Sort the work items in AG order. XFS locking 52 * order rules require us to lock buffers in AG order. 53 * - Create a log intent item for that type. 54 * - Attach it to the pending item. 55 * - Move the pending item from the dop_intake list to the [all …]
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