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/Linux-v5.10/Documentation/devicetree/bindings/regulator/
Dnvidia,tegra-regulators-coupling.txt4 NVIDIA Tegra SoC's have a mandatory voltage-coupling between regulators.
5 Thus on Tegra20 there are 3 coupled regulators and on NVIDIA Tegra30
9 ------------------------
11 On Tegra20 SoC's there are 3 coupled regulators: CORE, RTC and CPU.
16 ------------------------
18 On Tegra30 SoC's there are 2 coupled regulators: CORE and CPU. The CORE
24 - nvidia,tegra-core-regulator: Boolean property that designates regulator
25 as the "Core domain" voltage regulator.
26 - nvidia,tegra-rtc-regulator: Boolean property that designates regulator
27 as the "RTC domain" voltage regulator.
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Dregulator.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/regulator/regulator.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Liam Girdwood <lgirdwood@gmail.com>
11 - Mark Brown <broonie@kernel.org>
14 regulator-name:
15 description: A string used as a descriptive name for regulator outputs
18 regulator-min-microvolt:
21 regulator-max-microvolt:
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/Linux-v5.10/arch/arm/boot/dts/
Dtegra30-asus-nexus7-grouper-ti-pmic.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #include <dt-bindings/interrupt-controller/arm-gic.h>
4 #include <dt-bindings/gpio/gpio.h>
13 #interrupt-cells = <2>;
14 interrupt-controller;
16 ti,en-gpio-sleep = <0 0 1 0 0 0 0 0 0>;
17 ti,system-power-controller;
18 ti,sleep-keep-ck32k;
19 ti,sleep-enable;
21 #gpio-cells = <2>;
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Dtegra30-cardhu-a04.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include "tegra30-cardhu.dtsi"
5 #include "tegra30-cpu-opp.dtsi"
6 #include "tegra30-cpu-opp-microvolt.dtsi"
12 compatible = "nvidia,cardhu-a04", "nvidia,cardhu", "nvidia,tegra30";
16 power-gpios = <&gpio TEGRA_GPIO(D, 3) GPIO_ACTIVE_HIGH>;
17 bus-width = <4>;
18 keep-power-in-suspend;
21 ddr_reg: regulator@100 {
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Dtegra30-asus-nexus7-grouper-maxim-pmic.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #include <dt-bindings/interrupt-controller/arm-gic.h>
4 #include <dt-bindings/gpio/gpio.h>
5 #include <dt-bindings/mfd/max77620.h>
14 #interrupt-cells = <2>;
15 interrupt-controller;
17 #gpio-cells = <2>;
18 gpio-controller;
20 system-power-controller;
22 pinctrl-names = "default";
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Dtegra20-paz00.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/input.h>
6 #include "tegra20-cpu-opp.dtsi"
7 #include "tegra20-cpu-opp-microvolt.dtsi"
21 stdout-path = "serial0:115200n8";
40 vdd-supply = <&hdmi_vdd_reg>;
41 pll-supply = <&hdmi_pll_reg>;
43 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
44 nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
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Dexynos5422-odroid-core.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Hardkernel Odroid XU3/XU3-Lite/XU4/HC1 boards core device tree source
6 * Copyright (c) 2013-2017 Samsung Electronics Co., Ltd.
10 #include <dt-bindings/clock/samsung,s2mps11.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/gpio/gpio.h>
14 #include "exynos5422-cpus.dtsi"
23 stdout-path = "serial2:115200n8";
27 compatible = "samsung,secure-firmware";
31 fixed-rate-clocks {
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Dtegra20-acer-a500-picasso.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/gpio-keys.h>
5 #include <dt-bindings/input/input.h>
6 #include <dt-bindings/thermal/thermal.h>
9 #include "tegra20-cpu-opp.dtsi"
10 #include "tegra20-cpu-opp-microvolt.dtsi"
31 * pre-existing /chosen node to be available to insert the
40 reserved-memory {
41 #address-cells = <1>;
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Dexynos5800-peach-pi.dts1 // SPDX-License-Identifier: GPL-2.0
8 /dts-v1/;
9 #include <dt-bindings/input/input.h>
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/clock/maxim,max77802.h>
13 #include <dt-bindings/regulator/maxim,max77802.h>
14 #include <dt-bindings/sound/samsung-i2s.h>
16 #include "exynos5420-cpus.dtsi"
21 compatible = "google,pi-rev16",
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Dtegra30-beaver.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
5 #include "tegra30-cpu-opp.dtsi"
6 #include "tegra30-cpu-opp-microvolt.dtsi"
19 stdout-path = "serial0:115200n8";
29 avdd-pexa-supply = <&ldo1_reg>;
30 vdd-pexa-supply = <&ldo1_reg>;
31 avdd-pexb-supply = <&ldo1_reg>;
32 vdd-pexb-supply = <&ldo1_reg>;
33 avdd-pex-pll-supply = <&ldo1_reg>;
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/Linux-v5.10/drivers/regulator/
Dof_regulator.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * OF helpers for regulator framework
12 #include <linux/regulator/machine.h>
13 #include <linux/regulator/driver.h>
14 #include <linux/regulator/of_regulator.h>
19 [PM_SUSPEND_STANDBY] = "regulator-state-standby",
20 [PM_SUSPEND_MEM] = "regulator-state-mem",
21 [PM_SUSPEND_MAX] = "regulator-state-disk",
29 struct regulation_constraints *constraints = &(*init_data)->constraints; in of_get_regulation_constraints()
37 n_phandles = of_count_phandle_with_args(np, "regulator-coupled-with", in of_get_regulation_constraints()
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/Linux-v5.10/include/linux/regulator/
Dmachine.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * machine.h -- SoC Regulator support, machine/board driver API.
9 * Regulator Machine/Board Interface.
15 #include <linux/regulator/consumer.h>
18 struct regulator;
21 * Regulator operation constraint flags. These flags are used to enable
22 * certain regulator operations and can be OR'ed together.
24 * VOLTAGE: Regulator output voltage can be changed by software on this
26 * CURRENT: Regulator output current can be changed by software on this
28 * MODE: Regulator operating mode can be changed by software on this
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/Linux-v5.10/drivers/soc/tegra/
Dregulators-tegra30.c1 // SPDX-License-Identifier: GPL-2.0+
4 * Copyright (C) 2019 GRATE-DRIVER project
7 * Copyright (C) 2010-2011 NVIDIA Corporation
10 #define pr_fmt(fmt) "tegra voltage-coupler: " fmt
15 #include <linux/regulator/coupler.h>
16 #include <linux/regulator/driver.h>
17 #include <linux/regulator/machine.h>
42 if (tegra->core_min_uV > 0) in tegra30_core_limit()
43 return tegra->core_min_uV; in tegra30_core_limit()
49 core_max_uV = max(core_cur_uV, 1200000); in tegra30_core_limit()
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Dregulators-tegra20.c1 // SPDX-License-Identifier: GPL-2.0+
4 * Copyright (C) 2019 GRATE-DRIVER project
7 * Copyright (C) 2010-2011 NVIDIA Corporation
10 #define pr_fmt(fmt) "tegra voltage-coupler: " fmt
15 #include <linux/regulator/coupler.h>
16 #include <linux/regulator/driver.h>
17 #include <linux/regulator/machine.h>
41 if (tegra->core_min_uV > 0) in tegra20_core_limit()
42 return tegra->core_min_uV; in tegra20_core_limit()
48 core_max_uV = max(core_cur_uV, 1200000); in tegra20_core_limit()
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