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/Linux-v6.1/drivers/i2c/muxes/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
10 tristate "GPIO-based I2C arbitration"
20 will be called i2c-arb-gpio-challenge.
23 tristate "GPIO-based I2C multiplexer"
27 GPIO based I2C multiplexer. This driver provides access to
32 will be called i2c-mux-gpio.
42 by a MUX-controller from the MUX subsystem.
45 will be called i2c-mux-gpmux.
56 will be called i2c-mux-ltc4306.
65 will be called i2c-mux-pca9541.
[all …]
/Linux-v6.1/Documentation/x86/x86_64/
Dfsgs.rst1 .. SPDX-License-Identifier: GPL-2.0
7 memory can use segment register based addressing mode. The following
10 Segment-register:Byte-address
12 The segment base address is added to the Byte-address to compute the
14 instances of data with the identical Byte-address, i.e. the same code. The
15 selection of a particular instance is purely based on the base-address in
16 the segment register.
18 In 32-bit mode the CPU provides 6 segments, which also support segment
21 In 64-bit mode the CS/SS/DS/ES segments are ignored and the base address is
23 still functional in 64-bit mode.
[all …]
/Linux-v6.1/arch/arm64/kvm/hyp/nvhe/
Dpkvm.c1 // SPDX-License-Identifier: GPL-2.0-only
13 * Set trap register values based on features in ID_AA64PFR0.
29 * Linux guests assume support for floating-point and Advanced SIMD. Do in pvm_init_traps_aa64pfr0()
54 vcpu->arch.hcr_el2 |= hcr_set; in pvm_init_traps_aa64pfr0()
55 vcpu->arch.hcr_el2 &= ~hcr_clear; in pvm_init_traps_aa64pfr0()
56 vcpu->arch.cptr_el2 |= cptr_set; in pvm_init_traps_aa64pfr0()
60 * Set trap register values based on features in ID_AA64PFR1.
74 vcpu->arch.hcr_el2 |= hcr_set; in pvm_init_traps_aa64pfr1()
75 vcpu->arch.hcr_el2 &= ~hcr_clear; in pvm_init_traps_aa64pfr1()
79 * Set trap register values based on features in ID_AA64DFR0.
[all …]
/Linux-v6.1/Documentation/devicetree/bindings/net/
Dapm-xgene-enet.txt1 APM X-Gene SoC Ethernet nodes
3 Ethernet nodes are defined to describe on-chip ethernet interfaces in
4 APM X-Gene SoC.
7 - compatible: Should state binding information from the following list,
8 - "apm,xgene-enet": RGMII based 1G interface
9 - "apm,xgene1-sgenet": SGMII based 1G interface
10 - "apm,xgene1-xgenet": XFI based 10G interface
11 - reg: Address and length of the register set for the device. It contains the
12 information of registers in the same order as described by reg-names
13 - reg-names: Should contain the register set names
[all …]
/Linux-v6.1/drivers/pci/controller/
Dpcie-iproc.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (C) 2014-2015 Broadcom Corporation
10 * enum iproc_pcie_type - iProc PCIe interface type
11 * @IPROC_PCIE_PAXB_BCMA: BCMA-based host controllers
12 * @IPROC_PCIE_PAXB: PAXB-based host controllers for
14 * @IPROC_PCIE_PAXB_V2: PAXB-based host controllers for Stingray SoCs
15 * @IPROC_PCIE_PAXC: PAXC-based host controllers
16 * @IPROC_PCIE_PAXC_V2: PAXC-based host controllers (second generation)
33 * struct iproc_pcie_ob - iProc PCIe outbound mapping
44 * struct iproc_pcie_ib - iProc PCIe inbound mapping
[all …]
/Linux-v6.1/Documentation/powerpc/
Ddscr.rst2 DSCR (Data Stream Control Register)
5 DSCR register in powerpc allows user to have some control of prefetch of data
21 dscr_default /* per-CPU DSCR default value */
29 Scheduler will write the per-CPU DSCR default which is stored in the
30 CPU's PACA value into the register if the thread has dscr_inherit value
34 now be contained in thread struct's dscr into the register instead of
35 the per-CPU default PACA based DSCR value.
42 - Global DSCR default: /sys/devices/system/cpu/dscr_default
43 - CPU specific DSCR default: /sys/devices/system/cpu/cpuN/dscr
48 value into every CPU's DSCR register right away and updates the current
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/Linux-v6.1/Documentation/driver-api/media/
Dcamera-sensor.rst1 .. SPDX-License-Identifier: GPL-2.0
6 CSI-2 and parallel (BT.601 and BT.656) busses
7 ---------------------------------------------
9 Please see :ref:`transmitter-receiver`.
12 ---------------
15 divisors. The clock tree is generally configured by the driver based on a few
23 elsewhere. Therefore only the pre-determined frequencies are configurable by the
29 Read the ``clock-frequency`` _DSD property to denote the frequency. The driver
35 The currently preferred way to achieve this is using ``assigned-clocks``,
36 ``assigned-clock-parents`` and ``assigned-clock-rates`` properties. See
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/Linux-v6.1/Documentation/admin-guide/
Dmono.rst2 -----------------------------------------
4 To configure Linux to automatically execute Mono-based .NET binaries
8 This will allow you to execute Mono-based .NET binaries just like any
15 https://www.mono-project.com/download/
19 https://www.mono-project.com/docs/compiling-mono/linux/
36 .. code-block:: sh
39 if [ ! -e /proc/sys/fs/binfmt_misc/register ]; then
44 # or during normal boot up (systemd-based systems).
47 mount -t binfmt_misc none /proc/sys/fs/binfmt_misc
50 # Register support for .NET CLR binaries
[all …]
/Linux-v6.1/Documentation/trace/
Duser_events.rst2 user_events: User-based Event Tracing
8 --------
9 User based trace events allow user processes to create events and trace data
14 /sys/kernel/debug/tracing/user_events_status and can both register and write
17 Programs can also use /sys/kernel/debug/tracing/dynamic_events to register and
18 delete user based events via the u: prefix. The format of the command to
21 Typically programs will register a set of events that they wish to expose to
24 the status bit. This describes which bit in little-endian format in the
36 -----------
55 User based events show up under tracefs like any other event under the
[all …]
/Linux-v6.1/drivers/watchdog/
Dat91sam9_wdt.h1 /* SPDX-License-Identifier: GPL-2.0+ */
9 * Watchdog Timer (WDT) - System peripherals regsters.
10 * Based on AT91SAM9261 datasheet revision D.
11 * Based on SAM9X60 datasheet.
20 #define AT91_WDT_CR 0x00 /* Watchdog Control Register */
24 #define AT91_WDT_MR 0x04 /* Watchdog Mode Register */
39 #define AT91_WDT_SR 0x08 /* Watchdog Status Register */
43 /* Watchdog Timer Value Register */
46 /* Watchdog Window Level Register */
52 /* Interrupt Enable Register */
[all …]
/Linux-v6.1/Documentation/scsi/
Dhptiop.rst1 .. SPDX-License-Identifier: GPL-2.0
8 Controller Register Map
9 -----------------------
11 For RR44xx Intel IOP based adapters, the controller IOP is accessed via PCI BAR0 and BAR2
14 BAR0 offset Register
21 BAR2 offset Register
23 0x10 Inbound Message Register 0
24 0x14 Inbound Message Register 1
25 0x18 Outbound Message Register 0
26 0x1C Outbound Message Register 1
[all …]
/Linux-v6.1/drivers/net/can/sja1000/
Dplx_pci.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2008-2010 Pavel Cheblakov <P.B.Cheblakov@inp.nsk.su>
7 * Copyright (C) 2008 Markus Plessing <plessing@ems-wuensche.com>
8 * Copyright (C) 2008 Sebastian Haas <haas@ems-wuensche.com>
26 MODULE_DESCRIPTION("Socket-CAN driver for PLX90xx PCI-bridge cards with "
37 /* Pointer to device-dependent reset function */
47 * Control register
70 * Setting the OCR register to 0xDA is a good idea.
71 * This means normal output mode, push-pull and the correct polarity.
79 * In the CDR register, you should set CBP to 1.
[all …]
/Linux-v6.1/drivers/staging/rtl8192u/
Dr8192U_hw.h1 /* SPDX-License-Identifier: GPL-2.0 */
4 * Copyright (C) Andrea Merello 2004-2005 <andrea.merello@gmail.com>
6 * Parts of this driver are based on the GPL part of the
8 * Parts of this driver are based on the rtl8180 driver skeleton
10 * Parts of this driver are based on the Intel Pro Wireless
19 /* this file contains register definitions for the rtl8187 MAC controller */
72 BB_GLOBAL_RESET = 0x020, // BasebandGlobal Reset Register
73 BSSIDR = 0x02E, // BSSID Register
74 CMDR = 0x037, // Command register
77 SIFS = 0x03E, // SIFS register
[all …]
/Linux-v6.1/drivers/scsi/aic7xxx/
DKconfig.aic7xxx1 # SPDX-License-Identifier: GPL-2.0-only
4 # $Id: //depot/linux-aic79xx-2.5.0/drivers/scsi/aic7xxx/Kconfig.aic7xxx#7 $
7 tristate "Adaptec AIC7xxx Fast -> U160 support"
12 based SCSI controllers as well as the aic7770 based EISA and VLB
13 SCSI controllers (the 274x and 284x series). For AAA and ARO based
29 vary this number based on device behavior. For devices with a
33 Due to resource allocation issues in the Linux SCSI mid-layer, using
43 int "Initial bus reset delay in milli-seconds"
80 are defined in the drivers/scsi/aic7xxx/aic7xxx.h - search for the
88 Compile in register value tables for the output of expanded register
/Linux-v6.1/drivers/gpio/
Dgpio-ich.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Intel ICH6-10, Series 5 and 6, Atom C2000 (Avoton/Rangeley) GPIO driver
18 * GPIO register offsets in GPIO I/O space.
20 * LVLx registers. Logic in the read/write functions takes a register and
21 * an absolute bit number and determines the proper register offset and bit
22 * number in that register. For example, to read the value of GPIO bit 50
34 {0x00, 0x30, 0x40}, /* USE_SEL[1-3] offsets */
35 {0x04, 0x34, 0x44}, /* IO_SEL[1-3] offsets */
36 {0x0c, 0x38, 0x48}, /* LVL[1-3] offsets */
54 #define ICHX_WRITE(val, reg, base_res) outl(val, (reg) + (base_res)->start)
[all …]
/Linux-v6.1/Documentation/devicetree/bindings/
Dcommon-properties.txt5 ----------
13 - big-endian: Boolean; force big endian register accesses
16 - little-endian: Boolean; force little endian register accesses
19 - native-endian: Boolean; always use register accesses matched to the
20 endianness of the kernel binary (e.g. LE vmlinux -> readl/writel,
21 BE vmlinux -> ioread32be/iowrite32be). In this case no byte swaps
22 will ever be performed. Use this if the hardware "self-adjusts"
23 register endianness based on the CPU's configured endianness.
27 In such cases, little-endian is the preferred default, but it is not
28 a requirement. Some implementations assume that little-endian is
[all …]
/Linux-v6.1/drivers/net/wireless/intersil/p54/
Dp54pci.h1 /* SPDX-License-Identifier: GPL-2.0-only */
7 * Defines for PCI based mac80211 Prism54 driver
11 * Based on the islsm (softmac prism54) driver, which is:
12 * Copyright 2004-2006 Jean-Baptiste Note <jbnote@gmail.com>, et al.
15 /* Device Interrupt register bits */
28 /* Interrupt Identification/Acknowledge/Enable register bits */
36 /* Control/Status register bits */
68 /* usb backend only needs the register defines above */
86 #define P54P_READ(r) (__force __le32)__raw_readl(&priv->map->r)
87 #define P54P_WRITE(r, val) __raw_writel((__force u32)(__le32)(val), &priv->map->r)
/Linux-v6.1/Documentation/driver-api/backlight/
Dlp855x-driver.rst15 -----------
28 Value: pwm based or register based
37 ------------------------
44 Value of DEVICE CONTROL register.
58 1) lp8552 platform data: i2c register mode with new eeprom data::
68 .name = "lcd-bl",
/Linux-v6.1/Documentation/devicetree/bindings/arm/bcm/
Dbrcm,brcmstb.txt2 -----------------------------------------------
3 Boards with Broadcom Brahma15 ARM-based BCMxxxx (generally BCM7xxx variants)
7 - compatible: "brcm,bcm<chip_id>", "brcm,brcmstb"
11 #address-cells = <2>;
12 #size-cells = <2>;
16 Further, syscon nodes that map platform-specific registers used for general
19 - compatible: "brcm,bcm<chip_id>-sun-top-ctrl", "syscon"
20 - compatible: "brcm,bcm<chip_id>-cpu-biu-ctrl",
21 "brcm,brcmstb-cpu-biu-ctrl",
23 - compatible: "brcm,bcm<chip_id>-hif-continuation", "syscon"
[all …]
/Linux-v6.1/arch/arm/mach-davinci/
Dmux.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Utility to set the DAVINCI MUX register from a table in mux.h
7 * Based on linux/arch/arm/plat-omap/mux.c:
8 * Copyright (C) 2003 - 2005 Nokia Corporation
29 * Sets the DAVINCI MUX register based on the table
40 if (WARN_ON(!soc_info->pinmux_pins)) in davinci_cfg_reg()
41 return -ENODEV; in davinci_cfg_reg()
44 pinmux_base = ioremap(soc_info->pinmux_base, SZ_4K); in davinci_cfg_reg()
46 return -ENOMEM; in davinci_cfg_reg()
49 if (index >= soc_info->pinmux_pins_num) { in davinci_cfg_reg()
[all …]
/Linux-v6.1/include/drm/
Ddrm_module.h1 /* SPDX-License-Identifier: MIT */
15 * initialization and shutdown. The provided helpers act like bus-specific
22 * .. code-block:: c
29 * The generated code will test if DRM drivers are enabled and register
41 return -ENODEV; in drm_pci_register_driver()
47 * drm_module_pci_driver - Register a DRM driver for PCI-based devices
64 if (drm_firmware_drivers_only() && modeset == -1) in drm_pci_register_driver_if_modeset()
65 return -ENODEV; in drm_pci_register_driver_if_modeset()
67 return -ENODEV; in drm_pci_register_driver_if_modeset()
79 * drm_module_pci_driver_if_modeset - Register a DRM driver for PCI-based devices
[all …]
/Linux-v6.1/Documentation/virt/kvm/devices/
Darm-vgic-v3.rst1 .. SPDX-License-Identifier: GPL-2.0
9 - KVM_DEV_TYPE_ARM_VGIC_V3 ARM Generic Interrupt Controller v3.0
12 will act as the VM interrupt controller, requiring emulated user-space devices
23 KVM_VGIC_V3_ADDR_TYPE_DIST (rw, 64-bit)
25 register mappings. Only valid for KVM_DEV_TYPE_ARM_VGIC_V3.
28 KVM_VGIC_V3_ADDR_TYPE_REDIST (rw, 64-bit)
30 redistributor register mappings. There are two 64K pages for each
35 KVM_VGIC_V3_ADDR_TYPE_REDIST_REGION (rw, 64-bit)
38 bits: | 63 .... 52 | 51 .... 16 | 15 - 12 |11 - 0
41 - index encodes the unique redistributor region index
[all …]
/Linux-v6.1/arch/arm/mach-omap2/
Domap-headsmp.S1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 2009-2014 Texas Instruments, Inc.
10 * Interface functions needed for the SMP. This file is based on arm
40 * register AuxCoreBoot0.
58 .arch armv7-a
79 * register AuxCoreBoot0.
109 * GIC distributor control register has changed between
110 * CortexA9 r1pX and r2pX. The Control Register secure
113 * bit 1 == Non-Secure Enable
114 * The Non-Secure banked register has not changed
[all …]
/Linux-v6.1/drivers/rtc/
Drtc-rx4581.c1 // SPDX-License-Identifier: GPL-2.0-only
2 /* drivers/rtc/rtc-rx4581.c
6 * Based on:
7 * drivers/rtc/rtc-max6902.c
14 * and based on:
15 * drivers/rtc/rtc-rx8581.c
22 * Based on: rtc-pcf8563.c (An I2C driver for the Philips PCF8563 RTC)
23 * Copyright 2005-06 Tower Technologies
48 #define RX4581_REG_EXT 0x0D /* Extension Register */
49 #define RX4581_REG_FLAG 0x0E /* Flag Register */
[all …]
/Linux-v6.1/Documentation/devicetree/bindings/net/wireless/
Dqcom,ath10k.txt4 - compatible: Should be one of the following:
6 * "qcom,ipq4019-wifi"
7 * "qcom,wcn3990-wifi"
9 PCI based devices uses compatible string "qcom,ath10k" and takes calibration
10 data along with board specific data via "qcom,ath10k-calibration-data".
11 Rest of the properties are not applicable for PCI based devices.
13 AHB based devices (i.e. ipq4019) uses compatible string "qcom,ipq4019-wifi"
15 "qcom,ath10k-calibration-data"). It uses "qcom,ath10k-pre-calibration-data"
18 In general, entry "qcom,ath10k-pre-calibration-data" and
19 "qcom,ath10k-calibration-data" conflict with each other and only one
[all …]

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