/Linux-v5.4/drivers/clk/imx/ |
D | clk.h | 1 /* SPDX-License-Identifier: GPL-2.0 */ 6 #include <linux/clk-provider.h> 54 imx_clk_hw_cpu(name, parent_name, div, mux, pll, step)->clk 56 #define clk_register_gate2(dev, name, parent_name, flags, reg, bit_idx, \ argument 58 clk_hw_register_gate2(dev, name, parent_name, flags, reg, bit_idx, \ 59 cgr_val, clk_gate_flags, lock, share_count)->clk 62 imx_clk_hw_pllv3(type, name, parent_name, base, div_mask)->clk 64 #define imx_clk_pfd(name, parent_name, reg, idx) \ argument 65 imx_clk_hw_pfd(name, parent_name, reg, idx)->clk 67 #define imx_clk_gate_exclusive(name, parent, reg, shift, exclusive_mask) \ argument [all …]
|
D | clk-busy.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later 8 #include <linux/clk-provider.h> 15 static int clk_busy_wait(void __iomem *reg, u8 shift) in clk_busy_wait() argument 19 while (readl_relaxed(reg) & (1 << shift)) in clk_busy_wait() 21 return -ETIMEDOUT; in clk_busy_wait() 29 void __iomem *reg; member 30 u8 shift; member 45 return busy->div_ops->recalc_rate(&busy->div.hw, parent_rate); in clk_busy_divider_recalc_rate() 53 return busy->div_ops->round_rate(&busy->div.hw, rate, prate); in clk_busy_divider_round_rate() 62 ret = busy->div_ops->set_rate(&busy->div.hw, rate, parent_rate); in clk_busy_divider_set_rate() [all …]
|
/Linux-v5.4/drivers/memory/tegra/ |
D | tegra30.c | 1 // SPDX-License-Identifier: GPL-2.0-only 9 #include <dt-bindings/memory/tegra30-mc.h> 23 .reg = 0x228, 27 .reg = 0x2e8, 28 .shift = 0, 37 .reg = 0x228, 41 .reg = 0x2f4, 42 .shift = 0, 51 .reg = 0x228, 55 .reg = 0x2e8, [all …]
|
D | tegra114.c | 1 // SPDX-License-Identifier: GPL-2.0-only 9 #include <dt-bindings/memory/tegra114-mc.h> 23 .reg = 0x228, 27 .reg = 0x2e8, 28 .shift = 0, 37 .reg = 0x228, 41 .reg = 0x2f4, 42 .shift = 0, 51 .reg = 0x228, 55 .reg = 0x2e8, [all …]
|
D | tegra210.c | 1 // SPDX-License-Identifier: GPL-2.0-only 6 #include <dt-bindings/memory/tegra210-mc.h> 20 .reg = 0x228, 24 .reg = 0x2e8, 25 .shift = 0, 34 .reg = 0x228, 38 .reg = 0x2f4, 39 .shift = 0, 48 .reg = 0x228, 52 .reg = 0x2e8, [all …]
|
D | tegra124.c | 1 // SPDX-License-Identifier: GPL-2.0-only 9 #include <dt-bindings/memory/tegra124-mc.h> 43 .reg = 0x228, 47 .reg = 0x2e8, 48 .shift = 0, 57 .reg = 0x228, 61 .reg = 0x2f4, 62 .shift = 0, 71 .reg = 0x228, 75 .reg = 0x2e8, [all …]
|
/Linux-v5.4/arch/arm/boot/dts/ |
D | omap24xx-clocks.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only 9 #clock-cells = <0>; 10 compatible = "ti,composite-mux-clock"; 12 ti,bit-shift = <2>; 13 reg = <0x4>; 17 #clock-cells = <0>; 18 compatible = "ti,composite-clock"; 23 #clock-cells = <0>; 24 compatible = "ti,composite-mux-clock"; 26 ti,bit-shift = <6>; [all …]
|
D | omap3xxx-clocks.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only 9 #clock-cells = <0>; 10 compatible = "fixed-clock"; 11 clock-frequency = <16800000>; 15 #clock-cells = <0>; 16 compatible = "ti,mux-clock"; 18 reg = <0x0d40>; 22 #clock-cells = <0>; 23 compatible = "ti,divider-clock"; 25 ti,bit-shift = <6>; [all …]
|
D | omap2430-clocks.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only 10 #clock-cells = <0>; 11 compatible = "ti,composite-mux-clock"; 13 reg = <0x78>; 17 #clock-cells = <0>; 18 compatible = "ti,composite-clock"; 23 #clock-cells = <0>; 24 compatible = "ti,composite-mux-clock"; 26 ti,bit-shift = <2>; 27 reg = <0x78>; [all …]
|
D | omap34xx-omap36xx-clocks.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only 9 #clock-cells = <0>; 10 compatible = "fixed-factor-clock"; 12 clock-mult = <1>; 13 clock-div = <1>; 17 #clock-cells = <0>; 18 compatible = "ti,omap3-interface-clock"; 20 ti,bit-shift = <3>; 21 reg = <0x0a14>; 25 #clock-cells = <0>; [all …]
|
D | omap44xx-clocks.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only 9 #clock-cells = <0>; 10 compatible = "fixed-clock"; 11 clock-frequency = <59000000>; 15 #clock-cells = <0>; 16 compatible = "fixed-clock"; 17 clock-frequency = <12000000>; 21 #clock-cells = <0>; 22 compatible = "ti,gate-clock"; 24 ti,bit-shift = <8>; [all …]
|
D | omap2420-clocks.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only 10 #clock-cells = <0>; 11 compatible = "ti,composite-no-wait-gate-clock"; 13 ti,bit-shift = <15>; 14 reg = <0x0070>; 18 #clock-cells = <0>; 19 compatible = "ti,composite-mux-clock"; 21 ti,bit-shift = <8>; 22 reg = <0x0070>; 26 #clock-cells = <0>; [all …]
|
D | omap3430es1-clocks.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only 9 #clock-cells = <0>; 10 compatible = "ti,wait-gate-clock"; 12 reg = <0x0b10>; 13 ti,bit-shift = <0>; 17 #clock-cells = <0>; 18 compatible = "ti,divider-clock"; 20 ti,max-div = <7>; 21 reg = <0x0b40>; 22 ti,index-starts-at-one; [all …]
|
D | omap54xx-clocks.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only 9 #clock-cells = <0>; 10 compatible = "fixed-clock"; 11 clock-frequency = <12000000>; 15 #clock-cells = <0>; 16 compatible = "ti,gate-clock"; 18 ti,bit-shift = <8>; 19 reg = <0x0108>; 23 #clock-cells = <0>; 24 compatible = "fixed-clock"; [all …]
|
D | dra7xx-clocks.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only 9 #clock-cells = <0>; 10 compatible = "ti,dra7-atl-clock"; 15 #clock-cells = <0>; 16 compatible = "ti,dra7-atl-clock"; 21 #clock-cells = <0>; 22 compatible = "ti,dra7-atl-clock"; 27 #clock-cells = <0>; 28 compatible = "ti,dra7-atl-clock"; 33 #clock-cells = <0>; [all …]
|
/Linux-v5.4/drivers/bus/ |
D | da8xx-mstpri.c | 1 // SPDX-License-Identifier: GPL-2.0-only 24 * some changes (as is the case for the LCD controller on da850-lcdk - the 54 int reg; member 55 int shift; member 61 .reg = DA8XX_MSTPRI0_OFFSET, 62 .shift = 0, 66 .reg = DA8XX_MSTPRI0_OFFSET, 67 .shift = 4, 71 .reg = DA8XX_MSTPRI0_OFFSET, 72 .shift = 16, [all …]
|
/Linux-v5.4/drivers/regulator/ |
D | max8998.c | 1 // SPDX-License-Identifier: GPL-2.0+ 3 // max8998.c - Voltage regulator driver for the Maxim 8998 5 // Copyright (C) 2009-2010 Samsung Electronics 23 #include <linux/mfd/max8998-private.h> 37 int *reg, int *shift) in max8998_get_enable_register() argument 43 *reg = MAX8998_REG_ONOFF1; in max8998_get_enable_register() 44 *shift = 3 - (ldo - MAX8998_LDO2); in max8998_get_enable_register() 47 *reg = MAX8998_REG_ONOFF2; in max8998_get_enable_register() 48 *shift = 7 - (ldo - MAX8998_LDO6); in max8998_get_enable_register() 51 *reg = MAX8998_REG_ONOFF3; in max8998_get_enable_register() [all …]
|
/Linux-v5.4/arch/arm/mach-omap2/ |
D | vp.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */ 26 * struct omap_vp_ops - per-VP operations 36 * struct omap_vp_common - register data common to all VDDs 37 * @vpconfig_erroroffset_mask: ERROROFFSET bitmask in the PRM_VP*_CONFIG reg 38 * @vpconfig_errorgain_mask: ERRORGAIN bitmask in the PRM_VP*_CONFIG reg 39 * @vpconfig_initvoltage_mask: INITVOLTAGE bitmask in the PRM_VP*_CONFIG reg 40 * @vpconfig_timeouten: TIMEOUT bitmask in the PRM_VP*_CONFIG reg 41 * @vpconfig_initvdd: INITVDD bitmask in the PRM_VP*_CONFIG reg 42 * @vpconfig_forceupdate: FORCEUPDATE bitmask in the PRM_VP*_CONFIG reg 43 * @vpconfig_vpenable: VPENABLE bitmask in the PRM_VP*_CONFIG reg [all …]
|
/Linux-v5.4/drivers/clk/ |
D | clk-mux.c | 1 // SPDX-License-Identifier: GPL-2.0 5 * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org> 10 #include <linux/clk-provider.h> 20 * prepare - clk_prepare only ensures that parents are prepared 21 * enable - clk_enable only ensures that parents are enabled 22 * rate - rate is only affected by parent switching. No clk_set_rate support 23 * parent - parent is adjustable through clk_set_parent 28 if (mux->flags & CLK_MUX_BIG_ENDIAN) in clk_mux_readl() 29 return ioread32be(mux->reg); in clk_mux_readl() 31 return readl(mux->reg); in clk_mux_readl() [all …]
|
D | clk-axm5516.c | 1 // SPDX-License-Identifier: GPL-2.0-only 3 * drivers/clk/clk-axm5516.c 16 #include <linux/clk-provider.h> 18 #include <dt-bindings/clock/lsi,axm5516-clks.h> 22 * struct axxia_clk - Common struct to all Axxia clocks. 33 * struct axxia_pllclk - Axxia PLL generated clock. 35 * @reg: Offset into regmap for PLL control register 39 u32 reg; member 44 * axxia_pllclk_recalc - Calculate the PLL generated clock rate given the 55 regmap_read(aclk->regmap, pll->reg, &control); in axxia_pllclk_recalc() [all …]
|
/Linux-v5.4/drivers/clk/meson/ |
D | parm.h | 1 /* SPDX-License-Identifier: GPL-2.0 */ 13 #define PMASK(width) GENMASK(width - 1, 0) 14 #define SETPMASK(width, shift) GENMASK(shift + width - 1, shift) argument 15 #define CLRPMASK(width, shift) (~SETPMASK(width, shift)) argument 17 #define PARM_GET(width, shift, reg) \ argument 18 (((reg) & SETPMASK(width, shift)) >> (shift)) 19 #define PARM_SET(width, shift, reg, val) \ argument 20 (((reg) & CLRPMASK(width, shift)) | ((val) << (shift))) 22 #define MESON_PARM_APPLICABLE(p) (!!((p)->width)) 26 u8 shift; member [all …]
|
/Linux-v5.4/drivers/clk/sunxi-ng/ |
D | ccu_nkmp.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later 4 * Maxime Ripard <maxime.ripard@free-electrons.com> 7 #include <linux/clk-provider.h> 39 for (_k = nkmp->min_k; _k <= nkmp->max_k; _k++) { in ccu_nkmp_find_best() 40 for (_n = nkmp->min_n; _n <= nkmp->max_n; _n++) { in ccu_nkmp_find_best() 41 for (_m = nkmp->min_m; _m <= nkmp->max_m; _m++) { in ccu_nkmp_find_best() 42 for (_p = nkmp->min_p; _p <= nkmp->max_p; _p <<= 1) { in ccu_nkmp_find_best() 52 if ((rate - tmp_rate) < (rate - best_rate)) { in ccu_nkmp_find_best() 64 nkmp->n = best_n; in ccu_nkmp_find_best() 65 nkmp->k = best_k; in ccu_nkmp_find_best() [all …]
|
D | ccu_nkm.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later 4 * Maxime Ripard <maxime.ripard@free-electrons.com> 7 #include <linux/clk-provider.h> 26 for (_k = nkm->min_k; _k <= nkm->max_k; _k++) { in ccu_nkm_find_best() 27 for (_n = nkm->min_n; _n <= nkm->max_n; _n++) { in ccu_nkm_find_best() 28 for (_m = nkm->min_m; _m <= nkm->max_m; _m++) { in ccu_nkm_find_best() 35 if ((rate - tmp_rate) < (rate - best_rate)) { in ccu_nkm_find_best() 45 nkm->n = best_n; in ccu_nkm_find_best() 46 nkm->k = best_k; in ccu_nkm_find_best() 47 nkm->m = best_m; in ccu_nkm_find_best() [all …]
|
/Linux-v5.4/sound/pci/ac97/ |
D | ac97_patch.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 10 #define AC97_SINGLE_VALUE(reg,shift,mask,invert) \ argument 11 ((reg) | ((shift) << 8) | ((shift) << 12) | ((mask) << 16) | \ 13 #define AC97_PAGE_SINGLE_VALUE(reg,shift,mask,invert,page) \ argument 14 (AC97_SINGLE_VALUE(reg,shift,mask,invert) | (1<<25) | ((page) << 26)) 15 #define AC97_SINGLE(xname, reg, shift, mask, invert) \ argument 19 .private_value = AC97_SINGLE_VALUE(reg, shift, mask, invert) } 20 #define AC97_PAGE_SINGLE(xname, reg, shift, mask, invert, page) \ argument 24 .private_value = AC97_PAGE_SINGLE_VALUE(reg, shift, mask, invert, page) } 25 #define AC97_DOUBLE(xname, reg, shift_left, shift_right, mask, invert) \ argument [all …]
|
/Linux-v5.4/drivers/clk/mxs/ |
D | clk-frac.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later 6 #include <linux/clk-provider.h> 13 * struct clk_frac - mxs fractional divider clock 15 * @reg: register address 16 * @shift: the divider bit shift 18 * @busy: busy bit shift 25 void __iomem *reg; member 26 u8 shift; member 40 div = readl_relaxed(frac->reg) >> frac->shift; in clk_frac_recalc_rate() 41 div &= (1 << frac->width) - 1; in clk_frac_recalc_rate() [all …]
|