Searched +full:reg +full:- +full:io +full:- +full:width (Results 1 – 25 of 755) sorted by relevance
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/Linux-v5.4/arch/arm/boot/dts/ |
D | omap-zoom-common.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 6 #include "omap-gpmc-smsc911x.dtsi" 19 reg = <3 0 8>; /* CS3, offset 0, IO size 8 */ 20 bank-width = <2>; 21 reg-shift = <1>; 22 reg-io-width = <1>; 23 interrupt-parent = <&gpio4>; 25 clock-frequency = <1843200>; 26 current-speed = <115200>; 27 gpmc,mux-add-data = <0>; [all …]
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D | r9a06g032.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 9 #include <dt-bindings/interrupt-controller/arm-gic.h> 10 #include <dt-bindings/clock/r9a06g032-sysctrl.h> 14 #address-cells = <1>; 15 #size-cells = <1>; 18 #address-cells = <1>; 19 #size-cells = <0>; 23 compatible = "arm,cortex-a7"; 24 reg = <0>; 30 compatible = "arm,cortex-a7"; [all …]
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D | imx27-eukrea-cpuimx27.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-or-later 6 /dts-v1/; 15 reg = <0xa0000000 0x04000000>; 18 clk14745600: clk-uart { 19 compatible = "fixed-clock"; 20 #clock-cells = <0>; 21 clock-frequency = <14745600>; 26 pinctrl-names = "default"; 27 pinctrl-0 = <&pinctrl_fec>; 32 pinctrl-names = "default"; [all …]
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D | suniv-f1c100s.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR X11) 3 * Copyright 2018 Icenowy Zheng <icenowy@aosc.io> 8 #address-cells = <1>; 9 #size-cells = <1>; 10 interrupt-parent = <&intc>; 13 osc24M: clk-24M { 14 #clock-cells = <0>; 15 compatible = "fixed-clock"; 16 clock-frequency = <24000000>; 17 clock-output-names = "osc24M"; [all …]
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D | sun8i-r40.dtsi | 2 * Copyright 2017 Chen-Yu Tsai <wens@csie.org> 3 * Copyright 2017 Icenowy Zheng <icenowy@aosc.io> 5 * This file is dual-licensed: you can use it either under the terms 44 #include <dt-bindings/interrupt-controller/arm-gic.h> 45 #include <dt-bindings/clock/sun8i-de2.h> 46 #include <dt-bindings/clock/sun8i-r40-ccu.h> 47 #include <dt-bindings/reset/sun8i-r40-ccu.h> 48 #include <dt-bindings/reset/sun8i-de2.h> 51 #address-cells = <1>; 52 #size-cells = <1>; [all …]
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D | ox810se.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-or-later 3 * ox810se.dtsi - Device tree file for Oxford Semiconductor OX810SE SoC 8 #include <dt-bindings/clock/oxsemi,ox810se.h> 9 #include <dt-bindings/reset/oxsemi,ox810se.h> 12 #address-cells = <1>; 13 #size-cells = <1>; 17 #address-cells = <0>; 18 #size-cells = <0>; 22 compatible = "arm,arm926ej-s"; 30 reg = <0x48000000 0x10000000>; [all …]
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/Linux-v5.4/arch/arm64/boot/dts/ti/ |
D | k3-j721e-main.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 5 * Copyright (C) 2016-2019 Texas Instruments Incorporated - http://www.ti.com/ 10 compatible = "mmio-sram"; 11 reg = <0x0 0x70000000 0x0 0x800000>; 12 #address-cells = <1>; 13 #size-cells = <1>; 16 atf-sram@0 { 17 reg = <0x0 0x20000>; 21 gic500: interrupt-controller@1800000 { 22 compatible = "arm,gic-v3"; [all …]
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/Linux-v5.4/arch/mips/boot/dts/netlogic/ |
D | xlp_evp.dts | 1 // SPDX-License-Identifier: GPL-2.0 6 /dts-v1/; 8 model = "netlogic,XLP-EVP"; 10 #address-cells = <2>; 11 #size-cells = <2>; 14 #address-cells = <2>; 15 #size-cells = <1>; 16 compatible = "simple-bus"; 23 reg = <0 0x30100 0xa00>; 24 reg-shift = <2>; [all …]
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D | xlp_fvp.dts | 1 // SPDX-License-Identifier: GPL-2.0 6 /dts-v1/; 8 model = "netlogic,XLP-FVP"; 10 #address-cells = <2>; 11 #size-cells = <2>; 14 #address-cells = <2>; 15 #size-cells = <1>; 16 compatible = "simple-bus"; 23 reg = <0 0x30100 0xa00>; 24 reg-shift = <2>; [all …]
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D | xlp_svp.dts | 1 // SPDX-License-Identifier: GPL-2.0 6 /dts-v1/; 8 model = "netlogic,XLP-SVP"; 10 #address-cells = <2>; 11 #size-cells = <2>; 14 #address-cells = <2>; 15 #size-cells = <1>; 16 compatible = "simple-bus"; 23 reg = <0 0x30100 0xa00>; 24 reg-shift = <2>; [all …]
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/Linux-v5.4/Documentation/devicetree/bindings/i2c/ |
D | i2c-ocores.txt | 1 Device tree configuration for i2c-ocores 4 - compatible : "opencores,i2c-ocores" 6 "sifive,fu540-c000-i2c", "sifive,i2c0" 8 FU540-C000 SoC. Please refer to sifive-blocks-ip-versioning.txt 10 - reg : bus address start and address range size of device 11 - clocks : handle to the controller clock; see the note below. 12 Mutually exclusive with opencores,ip-clock-frequency 13 - opencores,ip-clock-frequency: frequency of the controller clock in Hz; 15 - #address-cells : should be <1> 16 - #size-cells : should be <0> [all …]
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/Linux-v5.4/Documentation/devicetree/bindings/serial/ |
D | snps-dw-apb-uart.yaml | 1 # SPDX-License-Identifier: GPL-2.0 3 --- 4 $id: http://devicetree.org/schemas/serial/snps-dw-apb-uart.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Rob Herring <robh@kernel.org> 13 - $ref: /schemas/serial.yaml# 18 - items: 19 - enum: 20 - renesas,r9a06g032-uart 21 - renesas,r9a06g033-uart [all …]
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/Linux-v5.4/arch/arm64/boot/dts/realtek/ |
D | rtd129x.dtsi | 4 * Copyright (c) 2016-2017 Andreas Färber 6 * SPDX-License-Identifier: (GPL-2.0+ OR MIT) 15 #include <dt-bindings/interrupt-controller/arm-gic.h> 18 interrupt-parent = <&gic>; 19 #address-cells = <1>; 20 #size-cells = <1>; 22 arm_pmu: arm-pmu { 23 compatible = "arm,cortex-a53-pmu"; 28 compatible = "simple-bus"; 29 #address-cells = <1>; [all …]
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/Linux-v5.4/arch/arc/boot/dts/ |
D | vdk_axs10x_mb.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only 5 * Copyright (C) 2013-15 Synopsys, Inc. (www.synopsys.com) 10 compatible = "simple-bus"; 11 #address-cells = <1>; 12 #size-cells = <1>; 14 interrupt-parent = <&mb_intc>; 18 compatible = "fixed-clock"; 19 clock-frequency = <50000000>; 20 #clock-cells = <0>; 24 compatible = "fixed-clock"; [all …]
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/Linux-v5.4/arch/arm64/boot/dts/bitmain/ |
D | bm1880.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 7 #include <dt-bindings/interrupt-controller/arm-gic.h> 8 #include <dt-bindings/reset/bitmain,bm1880-reset.h> 12 interrupt-parent = <&gic>; 13 #address-cells = <2>; 14 #size-cells = <2>; 17 #address-cells = <1>; 18 #size-cells = <0>; 22 compatible = "arm,cortex-a53"; 23 reg = <0x0>; [all …]
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/Linux-v5.4/arch/arm64/boot/dts/al/ |
D | alpine-v2.dtsi | 4 * Antoine Tenart <antoine.tenart@free-electrons.com> 16 * - Redistributions of source code must retain the above 20 * - Redistributions in binary form must reproduce the above 35 /dts-v1/; 37 #include <dt-bindings/interrupt-controller/arm-gic.h> 41 compatible = "al,alpine-v2"; 42 #address-cells = <2>; 43 #size-cells = <2>; 46 #address-cells = <2>; 47 #size-cells = <0>; [all …]
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/Linux-v5.4/Documentation/devicetree/bindings/net/ |
D | smsc911x.txt | 1 * Smart Mixed-Signal Connectivity (SMSC) LAN911x/912x Controller 4 - compatible : Should be "smsc,lan<model>", "smsc,lan9115" 5 - reg : Address and length of the io space for SMSC LAN 6 - interrupts : one or two interrupt specifiers 7 - The first interrupt is the SMSC LAN interrupt line 8 - The second interrupt (if present) is the PME (power 11 - phy-mode : See ethernet.txt file in the same directory 14 - reg-shift : Specify the quantity to shift the register offsets by 15 - reg-io-width : Specify the size (in bytes) of the IO accesses that 18 - smsc,irq-active-high : Indicates the IRQ polarity is active-high [all …]
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D | gpmc-eth.txt | 4 General-Purpose Memory Controller can be used to connect Pseudo-SRAM devices 12 Documentation/devicetree/bindings/memory-controllers/omap-gpmc.txt 18 Child nodes need to specify the GPMC bus address width using the "bank-width" 20 specify the I/O registers address width. Even when the GPMC has a maximum 16-bit 21 address width, it supports devices with 32-bit word registers. 23 OMAP2+ board, "bank-width = <2>;" and "reg-io-width = <4>;". 26 - bank-width: Address width of the device in bytes. GPMC supports 8-bit 27 and 16-bit devices and so must be either 1 or 2 bytes. 28 - compatible: Compatible string property for the ethernet child device. 29 - gpmc,cs-on-ns: Chip-select assertion time [all …]
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/Linux-v5.4/arch/mips/boot/dts/mti/ |
D | sead3.dts | 1 // SPDX-License-Identifier: GPL-2.0 2 /dts-v1/; 8 #include <dt-bindings/interrupt-controller/mips-gic.h> 11 #address-cells = <1>; 12 #size-cells = <1>; 13 compatible = "mti,sead-3"; 14 model = "MIPS SEAD-3"; 17 stdout-path = "serial1:115200"; 33 reg = <0x0 0x08000000>; 36 cpu_intc: interrupt-controller { [all …]
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/Linux-v5.4/Documentation/devicetree/bindings/memory-controllers/ |
D | exynos-srom.txt | 4 - compatible : Should contain "samsung,exynos4210-srom". 6 - reg: offset and length of the register set 12 - #address-cells: Must be set to 2 to allow device address translation. 15 - #size-cells: Must be set to 1 to allow device size passing 17 - ranges: Must be set up to reflect the memory layout with four integer values 19 <bank-number> 0 <parent address of bank> <size> 21 Sub-nodes: 27 - reg: bank number, base address (relative to start of the bank) and size of 31 - samsung,srom-timing : array of 6 integers, specifying bank timings in the 35 Tacp : Page mode access cycle at Page mode (0 - 15) [all …]
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/Linux-v5.4/drivers/irqchip/ |
D | irq-renesas-intc-irqpin.c | 1 // SPDX-License-Identifier: GPL-2.0 14 #include <linux/io.h> 36 * SENSE is read-write 32-bit with 2-bits or 4-bits per IRQ (*) 37 * PRIO is read-write 32-bit with 4-bits per IRQ (**) 38 * SOURCE is read-only 32-bit or 8-bit with 1-bit per IRQ (***) 39 * MASK is write-only 32-bit or 8-bit with 1-bit per IRQ (***) 40 * CLEAR is write-only 32-bit or 8-bit with 1-bit per IRQ (***) 42 * (*) May be accessed by more than one driver instance - lock needed 43 * (**) Read-modify-write access by one driver instance - lock needed 44 * (***) Accessed by one driver instance only - no locking needed [all …]
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/Linux-v5.4/drivers/clk/mxs/ |
D | clk-frac.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later 6 #include <linux/clk-provider.h> 8 #include <linux/io.h> 13 * struct clk_frac - mxs fractional divider clock 15 * @reg: register address 17 * @width: the divider bit width 25 void __iomem *reg; member 27 u8 width; member 40 div = readl_relaxed(frac->reg) >> frac->shift; in clk_frac_recalc_rate() 41 div &= (1 << frac->width) - 1; in clk_frac_recalc_rate() [all …]
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/Linux-v5.4/Documentation/devicetree/bindings/display/rockchip/ |
D | dw_hdmi-rockchip.txt | 9 following device-specific properties. 14 - compatible: should be one of the following: 15 "rockchip,rk3228-dw-hdmi" 16 "rockchip,rk3288-dw-hdmi" 17 "rockchip,rk3328-dw-hdmi" 18 "rockchip,rk3399-dw-hdmi" 19 - reg: See dw_hdmi.txt. 20 - reg-io-width: See dw_hdmi.txt. Shall be 4. 21 - interrupts: HDMI interrupt number 22 - clocks: See dw_hdmi.txt. [all …]
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/Linux-v5.4/arch/powerpc/boot/dts/fsl/ |
D | gef_ppc9a.dts | 1 // SPDX-License-Identifier: GPL-2.0-or-later 14 * Compiled with dtc -I dts -O dtb -o gef_ppc9a.dtb gef_ppc9a.dts 17 /include/ "mpc8641si-pre.dtsi" 25 reg = <0x0 0x40000000>; // set by uboot 29 reg = <0xfef05000 0x1000>; 37 6 0 0xfd000000 0x00800000 // IO FPGA (8-bit) 38 7 0 0xfd800000 0x00800000>; // IO FPGA (32-bit) 42 compatible = "gef,ppc9a-firmware-mirror", "cfi-flash"; 43 reg = <0x0 0x0 0x1000000>; 44 bank-width = <4>; [all …]
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D | gef_sbc610.dts | 1 // SPDX-License-Identifier: GPL-2.0-or-later 14 * Compiled with dtc -I dts -O dtb -o gef_sbc610.dtb gef_sbc610.dts 17 /include/ "mpc8641si-pre.dtsi" 25 reg = <0x0 0x40000000>; // set by uboot 29 reg = <0xfef05000 0x1000>; 37 6 0 0xfd000000 0x00800000 // IO FPGA (8-bit) 38 7 0 0xfd800000 0x00800000>; // IO FPGA (32-bit) 42 compatible = "gef,sbc610-firmware-mirror", "cfi-flash"; 43 reg = <0x0 0x0 0x1000000>; 44 bank-width = <4>; [all …]
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