| /Linux-v6.1/drivers/gpu/drm/nouveau/nvkm/subdev/clk/ |
| D | pllgt215.c | 42 lM = (info->refclk + info->vco1.max_inputfreq) / info->vco1.max_inputfreq; in gt215_pll_calc()
44 hM = (info->refclk + info->vco1.min_inputfreq) / info->vco1.min_inputfreq; in gt215_pll_calc()
50 N = tmp / info->refclk; in gt215_pll_calc()
51 fN = tmp % info->refclk; in gt215_pll_calc()
54 if (fN >= info->refclk / 2) in gt215_pll_calc()
57 if (fN < info->refclk / 2) in gt215_pll_calc()
59 fN = tmp - (N * info->refclk); in gt215_pll_calc()
67 err = abs(freq - (info->refclk * N / M / *P)); in gt215_pll_calc()
75 *pfN = ((fN << 13) + info->refclk / 2) / info->refclk; in gt215_pll_calc()
86 return info->refclk * *pN / *pM / *P; in gt215_pll_calc()
|
| /Linux-v6.1/drivers/phy/ti/ |
| D | phy-dm816x-usb.c | 47 struct clk *refclk; member
77 if (clk_get_rate(phy->refclk) != 24000000) in dm816x_usb_phy_init()
78 dev_warn(phy->dev, "nonstandard phy refclk\n"); in dm816x_usb_phy_init()
124 clk_disable(phy->refclk); in dm816x_usb_phy_runtime_suspend()
135 error = clk_enable(phy->refclk); in dm816x_usb_phy_runtime_resume()
152 clk_disable(phy->refclk); in dm816x_usb_phy_runtime_resume()
227 phy->refclk = devm_clk_get(phy->dev, "refclk"); in dm816x_usb_phy_probe()
228 if (IS_ERR(phy->refclk)) in dm816x_usb_phy_probe()
229 return PTR_ERR(phy->refclk); in dm816x_usb_phy_probe()
230 error = clk_prepare(phy->refclk); in dm816x_usb_phy_probe()
[all …]
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| D | phy-ti-pipe3.c | 171 struct clk *refclk; member
607 phy->refclk = devm_clk_get(dev, "refclk"); in ti_pipe3_get_clk()
608 if (IS_ERR(phy->refclk)) { in ti_pipe3_get_clk()
609 dev_err(dev, "unable to get refclk\n"); in ti_pipe3_get_clk()
610 /* older DTBs have missing refclk in SATA PHY in ti_pipe3_get_clk()
614 return PTR_ERR(phy->refclk); in ti_pipe3_get_clk()
823 * Prevent auto-disable of refclk for SATA PHY due to Errata i783 in ti_pipe3_probe()
826 if (!IS_ERR(phy->refclk)) { in ti_pipe3_probe()
827 clk_prepare_enable(phy->refclk); in ti_pipe3_probe()
849 clk_disable_unprepare(phy->refclk); in ti_pipe3_remove()
[all …]
|
| /Linux-v6.1/Documentation/devicetree/bindings/usb/ |
| D | smsc,usb3503.yaml | 56 Clock used for driving REFCLK signal. If not provided the driver assumes
62 const: refclk
64 refclk-frequency:
67 Frequency of the REFCLK signal as defined by REF_SEL pins. If not
68 provided, driver will not set rate of the REFCLK signal and assume that a
91 clock-names = "refclk";
106 refclk-frequency = <19200000>;
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| D | octeon-usb.txt | 24 - cavium,refclk-type: type of the USB reference clock. Allowed values are
27 - refclk-frequency: deprecated, use "clock-frequency".
29 - refclk-type: deprecated, use "cavium,refclk-type".
54 cavium,refclk-type = "crystal";
|
| D | dwc3-cavium.txt | 18 refclk-frequency = <0x05f5e100>;
19 refclk-type-ss = "dlmc_ref_clk0";
20 refclk-type-hs = "dlmc_ref_clk0";
|
| /Linux-v6.1/drivers/gpu/drm/i915/display/ |
| D | intel_cdclk.c | 1230 u16 refclk; member
1237 { .refclk = 19200, .cdclk = 144000, .divider = 8, .ratio = 60 },
1238 { .refclk = 19200, .cdclk = 288000, .divider = 4, .ratio = 60 },
1239 { .refclk = 19200, .cdclk = 384000, .divider = 3, .ratio = 60 },
1240 { .refclk = 19200, .cdclk = 576000, .divider = 2, .ratio = 60 },
1241 { .refclk = 19200, .cdclk = 624000, .divider = 2, .ratio = 65 },
1246 { .refclk = 19200, .cdclk = 79200, .divider = 8, .ratio = 33 },
1247 { .refclk = 19200, .cdclk = 158400, .divider = 4, .ratio = 33 },
1248 { .refclk = 19200, .cdclk = 316800, .divider = 2, .ratio = 33 },
1253 { .refclk = 19200, .cdclk = 172800, .divider = 2, .ratio = 18 },
[all …]
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| D | intel_dpll.c | 231 /* LVDS 100mhz refclk limits. */
310 int pnv_calc_dpll_params(int refclk, struct dpll *clock) in pnv_calc_dpll_params() argument
316 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); in pnv_calc_dpll_params()
327 int i9xx_calc_dpll_params(int refclk, struct dpll *clock) in i9xx_calc_dpll_params() argument
333 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2); in i9xx_calc_dpll_params()
339 int vlv_calc_dpll_params(int refclk, struct dpll *clock) in vlv_calc_dpll_params() argument
345 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); in vlv_calc_dpll_params()
351 int chv_calc_dpll_params(int refclk, struct dpll *clock) in chv_calc_dpll_params() argument
357 clock->vco = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(refclk, clock->m), in chv_calc_dpll_params()
365 * Returns whether the given set of divisors are valid for a given refclk with
[all …]
|
| D | intel_dpll.h | 23 int vlv_calc_dpll_params(int refclk, struct dpll *clock);
24 int pnv_calc_dpll_params(int refclk, struct dpll *clock);
25 int i9xx_calc_dpll_params(int refclk, struct dpll *clock);
42 int chv_calc_dpll_params(int refclk, struct dpll *pll_clock);
|
| /Linux-v6.1/Documentation/devicetree/bindings/pinctrl/ |
| D | ralink,mt7620-pinctrl.yaml | 39 ephy, mdio, nd_sd, pa, pcie, rgmii1, rgmii2, spi refclk,
45 pwm1, refclk, sdmode, spi cs1, spis, uart0, uart1, uart2,
53 gpio, i2c, refclk, spi,
57 pcie refclk, pcie rst, pcm gpio, pcm i2s, pcm uartf,
58 rgmii1, rgmii2, sd, spi refclk, uartf, uartlite, wdt refclk,
|
| /Linux-v6.1/drivers/gpu/drm/gma500/ |
| D | gma_display.h | 44 int target, int refclk,
49 void (*clock)(int refclk, struct gma_clock_t *clock);
50 const struct gma_limit_t *(*limit)(struct drm_crtc *crtc, int refclk);
83 extern const struct gma_limit_t *gma_limit(struct drm_crtc *crtc, int refclk);
84 extern void gma_clock(int refclk, struct gma_clock_t *clock);
89 struct drm_crtc *crtc, int target, int refclk,
|
| D | oaktrail_crtc.c | 40 int refclk, struct gma_clock_t *best_clock);
44 int refclk, struct gma_clock_t *best_clock);
83 int refclk) in mrst_limit() argument
112 /** Derive the pixel clock for the given refclk and divisors for 8xx chips. */
113 static void mrst_lvds_clock(int refclk, struct gma_clock_t *clock) in mrst_lvds_clock() argument
115 clock->dot = (refclk * clock->m) / (14 * clock->p1); in mrst_lvds_clock()
127 int refclk, struct gma_clock_t *best_clock) in mrst_sdvo_find_best_pll() argument
152 actual_freq = (refclk * clock.m) / in mrst_sdvo_find_best_pll()
180 * Returns a set of divisors for the desired target clock with the given refclk,
185 int refclk, struct gma_clock_t *best_clock) in mrst_lvds_find_best_pll() argument
[all …]
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| D | cdv_intel_display.c | 24 int refclk, struct gma_clock_t *best_clock);
364 int refclk) in cdv_intel_limit() argument
372 if (refclk == 96000) in cdv_intel_limit()
378 if (refclk == 27000) in cdv_intel_limit()
383 if (refclk == 27000) in cdv_intel_limit()
392 static void cdv_intel_clock(int refclk, struct gma_clock_t *clock) in cdv_intel_clock() argument
396 clock->vco = (refclk * clock->m) / clock->n; in cdv_intel_clock()
402 int refclk, in cdv_intel_find_dp_pll() argument
410 switch (refclk) { in cdv_intel_find_dp_pll()
447 gma_crtc->clock_funcs->clock(refclk, &clock); in cdv_intel_find_dp_pll()
[all …]
|
| /Linux-v6.1/Documentation/devicetree/bindings/phy/ |
| D | fsl,imx8-pcie-phy.yaml | 37 fsl,refclk-pad-mode:
39 Specifies the mode of the refclk pad used. It can be UNUSED(PHY
41 is provided externally via the refclk pad) or OUTPUT(PHY refclock
42 is derived from SoC internal source and provided on the refclk pad).
69 - fsl,refclk-pad-mode
89 fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
|
| D | ti,phy-j721e-wiz.yaml | 84 refclk-dig:
120 "^pll[0|1]-refclk$":
217 pll0-refclk {
224 pll1-refclk {
231 cmn-refclk-dig-div {
241 refclk-dig {
|
| /Linux-v6.1/drivers/phy/xilinx/ |
| D | phy-zynqmp.c | 103 /* Refclk selection parameters */
192 * @refclk: reference clock index
201 unsigned int refclk; member
345 ssc = gtr_phy->dev->refclk_sscs[gtr_phy->refclk]; in xpsgtr_configure_pll()
352 if (gtr_phy->refclk != gtr_phy->lane) { in xpsgtr_configure_pll()
355 L0_REF_CLK_SEL_MASK, 1 << gtr_phy->refclk); in xpsgtr_configure_pll()
770 unsigned int refclk; in xpsgtr_xlate() local
799 refclk = args->args[3]; in xpsgtr_xlate()
800 if (refclk >= ARRAY_SIZE(gtr_dev->refclk_sscs) || in xpsgtr_xlate()
801 !gtr_dev->refclk_sscs[refclk]) { in xpsgtr_xlate()
[all …]
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| /Linux-v6.1/drivers/net/ethernet/arc/ |
| D | emac_rockchip.c | 32 struct clk *refclk; member
147 priv->refclk = devm_clk_get(dev, "macref"); in emac_rockchip_probe()
148 if (IS_ERR(priv->refclk)) { in emac_rockchip_probe()
150 PTR_ERR(priv->refclk)); in emac_rockchip_probe()
151 err = PTR_ERR(priv->refclk); in emac_rockchip_probe()
155 err = clk_prepare_enable(priv->refclk); in emac_rockchip_probe()
195 err = clk_set_rate(priv->refclk, 50000000); in emac_rockchip_probe()
241 clk_disable_unprepare(priv->refclk); in emac_rockchip_probe()
255 clk_disable_unprepare(priv->refclk); in emac_rockchip_remove()
|
| /Linux-v6.1/arch/mips/bcm63xx/ |
| D | clk.c | 421 CLKDEV_INIT("bcm63xx_uart.0", "refclk", &clk_periph),
422 CLKDEV_INIT("bcm63xx_uart.1", "refclk", &clk_periph),
438 CLKDEV_INIT("bcm63xx_uart.0", "refclk", &clk_periph),
439 CLKDEV_INIT("bcm63xx_uart.1", "refclk", &clk_periph),
452 CLKDEV_INIT("bcm63xx_uart.0", "refclk", &clk_periph),
466 CLKDEV_INIT("bcm63xx_uart.0", "refclk", &clk_periph),
480 CLKDEV_INIT("bcm63xx_uart.0", "refclk", &clk_periph),
495 CLKDEV_INIT("bcm63xx_uart.0", "refclk", &clk_periph),
496 CLKDEV_INIT("bcm63xx_uart.1", "refclk", &clk_periph),
514 CLKDEV_INIT("bcm63xx_uart.0", "refclk", &clk_periph),
[all …]
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| /Linux-v6.1/Documentation/devicetree/bindings/mips/cavium/ |
| D | uctl.txt | 16 - refclk-frequency: A single cell containing the reference clock
19 - refclk-type: A string describing the reference clock connection
30 refclk-frequency = <24000000>;
32 refclk-type = "crystal";
|
| /Linux-v6.1/drivers/gpu/drm/amd/display/dc/dcn32/ |
| D | dcn32_dccg.c | 148 if (src == REFCLK) in dccg32_set_dtbclk_p_src()
157 if (src == REFCLK) in dccg32_set_dtbclk_p_src()
166 if (src == REFCLK) in dccg32_set_dtbclk_p_src()
175 if (src == REFCLK) in dccg32_set_dtbclk_p_src()
259 * Assume refclk is sourced from xtalin in dccg32_get_dccg_ref_freq()
283 (src == REFCLK) ? 0 : 1, DPSTREAMCLK0_SRC_SEL, otg_inst); in dccg32_set_dpstreamclk()
287 (src == REFCLK) ? 0 : 1, DPSTREAMCLK1_SRC_SEL, otg_inst); in dccg32_set_dpstreamclk()
291 (src == REFCLK) ? 0 : 1, DPSTREAMCLK2_SRC_SEL, otg_inst); in dccg32_set_dpstreamclk()
295 (src == REFCLK) ? 0 : 1, DPSTREAMCLK3_SRC_SEL, otg_inst); in dccg32_set_dpstreamclk()
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| /Linux-v6.1/drivers/gpu/drm/amd/display/dc/dcn314/ |
| D | dcn314_dccg.c | 151 if (src == REFCLK) in dccg314_set_dtbclk_p_src()
160 if (src == REFCLK) in dccg314_set_dtbclk_p_src()
169 if (src == REFCLK) in dccg314_set_dtbclk_p_src()
178 if (src == REFCLK) in dccg314_set_dtbclk_p_src()
253 DPSTREAMCLK0_EN, (src == REFCLK) ? 0 : 1, in dccg314_set_dpstreamclk()
258 DPSTREAMCLK1_EN, (src == REFCLK) ? 0 : 1, in dccg314_set_dpstreamclk()
263 DPSTREAMCLK2_EN, (src == REFCLK) ? 0 : 1, in dccg314_set_dpstreamclk()
268 DPSTREAMCLK3_EN, (src == REFCLK) ? 0 : 1, in dccg314_set_dpstreamclk()
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| /Linux-v6.1/drivers/net/ethernet/ti/ |
| D | cpts.c | 571 err = clk_enable(cpts->refclk); in cpts_register()
592 clk_disable(cpts->refclk); in cpts_register()
612 clk_disable(cpts->refclk); in cpts_unregister()
621 freq = clk_get_rate(cpts->refclk); in cpts_calc_mult_shift()
662 refclk_np = of_get_child_by_name(node, "cpts-refclk-mux"); in cpts_of_mux_clk_setup()
664 /* refclk selection supported not for all SoCs */ in cpts_of_mux_clk_setup()
772 cpts->refclk = devm_get_clk_from_child(dev, node, "cpts"); in cpts_create()
773 if (IS_ERR(cpts->refclk)) in cpts_create()
775 cpts->refclk = devm_clk_get(dev, "cpts"); in cpts_create()
777 if (IS_ERR(cpts->refclk)) { in cpts_create()
[all …]
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| /Linux-v6.1/arch/arm/boot/dts/ |
| D | berlin2cd.dtsi | 51 refclk: oscillator { label
389 clocks = <&refclk>;
390 clock-names = "refclk";
446 clocks = <&refclk>;
453 clocks = <&refclk>;
461 clocks = <&refclk>;
486 clocks = <&refclk>;
497 clocks = <&refclk>;
507 clocks = <&refclk>;
532 clocks = <&refclk>;
[all …]
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| /Linux-v6.1/drivers/clk/berlin/ |
| D | bg2.c | 90 REFCLK, VIDEO_EXT0, enumerator
103 [REFCLK] = "refclk",
516 clk = of_clk_get_by_name(np, clk_names[REFCLK]); in berlin2_clock_setup()
518 clk_names[REFCLK] = __clk_get_name(clk); in berlin2_clock_setup()
530 clk_names[SYSPLL], clk_names[REFCLK], 0); in berlin2_clock_setup()
535 clk_names[MEMPLL], clk_names[REFCLK], 0); in berlin2_clock_setup()
540 clk_names[CPUPLL], clk_names[REFCLK], 0); in berlin2_clock_setup()
549 clk_names[REFCLK], avpll_flags, 0); in berlin2_clock_setup()
562 clk_names[REFCLK], BERLIN2_AVPLL_BIT_QUIRK | in berlin2_clock_setup()
577 parent_names[1] = clk_names[REFCLK]; in berlin2_clock_setup()
[all …]
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| /Linux-v6.1/Documentation/devicetree/bindings/clock/ |
| D | marvell,berlin.txt | 18 "refclk" for the SoCs oscillator input on all SoCs,
29 clocks = <&refclk>;
30 clock-names = "refclk";
|
