/Linux-v6.1/include/soc/at91/ |
D | at91sam9_ddrsdr.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 46 #define AT91_DDRSDRC_OCD (1 << 12) /* Off-Chip Driver [SAM9 Only] */ 48 #define AT91_DDRSDRC_ACTBST (1 << 18) /* Active Bank X to Burst Stop Read Access Bank Y [SAM9 Onl… 51 #define AT91_DDRSDRC_TRAS (0xf << 0) /* Active to Precharge delay */ 52 #define AT91_DDRSDRC_TRCD (0xf << 4) /* Row to Column delay */ 53 #define AT91_DDRSDRC_TWR (0xf << 8) /* Write recovery delay */ 54 #define AT91_DDRSDRC_TRC (0xf << 12) /* Row cycle delay */ 55 #define AT91_DDRSDRC_TRP (0xf << 16) /* Row precharge delay */ 57 #define AT91_DDRSDRC_TWTR (0x7 << 24) /* Internal Write to Read delay */ 58 #define AT91_DDRSDRC_RED_WRRD (0x1 << 27) /* Reduce Write to Read Delay [SAM9 Only] */ [all …]
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/Linux-v6.1/Documentation/devicetree/bindings/memory-controllers/ |
D | arm,pl172.txt | 5 - compatible: Must be "arm,primecell" and exactly one from 8 - reg: Must contains offset/length value for controller. 10 - #address-cells: Must be 2. The partition number has to be encoded in the 11 first address cell and it may accept values 0..N-1 12 (N - total number of partitions). The second cell is the 15 - #size-cells: Must be set to 1. 17 - ranges: Must contain one or more chip select memory regions. 19 - clocks: Must contain references to controller clocks. 21 - clock-names: Must contain "mpmcclk" and "apb_pclk". 23 - clock-ranges: Empty property indicating that child nodes can inherit [all …]
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D | ti,gpmc-child.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/memory-controllers/ti,gpmc-child.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Tony Lindgren <tony@atomide.com> 11 - Roger Quadros <rogerq@kernel.org> 24 gpmc,sync-clk-ps: 28 # Chip-select signal timings corresponding to GPMC_CONFIG2: 29 gpmc,cs-on-ns: 33 gpmc,cs-rd-off-ns: [all …]
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D | mvebu-devbus.txt | 9 - compatible: Armada 370/XP SoC are supported using the 10 "marvell,mvebu-devbus" compatible string. 13 "marvell,orion-devbus" compatible string. 15 - reg: A resource specifier for the register space. 20 - #address-cells: Must be set to 1 21 - #size-cells: Must be set to 1 22 - ranges: Must be set up to reflect the memory layout with four 23 integer values for each chip-select line in use: 28 - devbus,keep-config This property can optionally be used to keep 35 Read parameters: [all …]
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/Linux-v6.1/drivers/iio/common/ms_sensors/ |
D | ms_sensors_i2c.c | 1 // SPDX-License-Identifier: GPL-2.0-only 5 * Copyright (c) 2015 Measurement-Specialties 11 #include <linux/delay.h> 38 * ms_sensors_reset() - Reset function 41 * @delay: usleep minimal delay after reset command is issued 47 int ms_sensors_reset(void *cli, u8 cmd, unsigned int delay) in ms_sensors_reset() argument 54 dev_err(&client->dev, "Failed to reset device\n"); in ms_sensors_reset() 57 usleep_range(delay, delay + 1000); in ms_sensors_reset() 64 * ms_sensors_read_prom_word() - PROM word read function 66 * @cmd: PROM read cmd. Depends on device and prom id [all …]
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/Linux-v6.1/arch/sh/include/mach-common/mach/ |
D | sh2007.h | 1 /* SPDX-License-Identifier: GPL-2.0 */ 25 /* write-read/write-write delay (0-7:0,1,2,3,4,5,6,7) */ 28 /* different area, read-write delay (0-7:0,1,2,3,4,5,6,7) */ 31 /* same area, read-write delay (0-7:0,1,2,3,4,5,6,7) */ 34 /* different area, read-read delay (0-7:0,1,2,3,4,5,6,7) */ 37 /* same area, read-read delay (0-7:0,1,2,3,4,5,6,7) */ 40 /* burst count (0-3:4,8,16,32) */ 46 /* RD hold for SRAM (0-1:0,1) */ 49 /* Burst pitch (0-7:0,1,2,3,4,5,6,7) */ 52 /* Multiplex (0-1:0,1) */ [all …]
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/Linux-v6.1/arch/powerpc/platforms/pasemi/ |
D | gpio_mdio.c | 1 // SPDX-License-Identifier: GPL-2.0-only 3 * Copyright (C) 2006-2007 PA Semi, Inc 9 * Based on drivers/net/fs_enet/mii-bitbang.c. 25 #define DELAY 1 macro 34 #define MDC_PIN(bus) (((struct gpio_priv *)bus->priv)->mdc_pin) 35 #define MDIO_PIN(bus) (((struct gpio_priv *)bus->priv)->mdio_pin) 78 udelay(DELAY); in clock_out() 80 udelay(DELAY); in clock_out() 84 /* Utility to send the preamble, address, and register (common to read and write). */ 85 static void bitbang_pre(struct mii_bus *bus, int read, u8 addr, u8 reg) in bitbang_pre() argument [all …]
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/Linux-v6.1/Documentation/devicetree/bindings/mmc/ |
D | sdhci-sprd.txt | 1 * Spreadtrum SDHCI controller (sdhci-sprd) 7 and the properties used by the sdhci-sprd driver. 10 - compatible: Should contain "sprd,sdhci-r11". 11 - reg: physical base address of the controller and length. 12 - interrupts: Interrupts used by the SDHCI controller. 13 - clocks: Should contain phandle for the clock feeding the SDHCI controller 14 - clock-names: Should contain the following: 15 "sdio" - SDIO source clock (required) 16 "enable" - gate clock which used for enabling/disabling the device (required) 17 "2x_enable" - gate clock controlling the device for some special platforms (optional) [all …]
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D | fsl-imx-esdhc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/mmc/fsl-imx-esdhc.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Shawn Guo <shawnguo@kernel.org> 13 - $ref: "mmc-controller.yaml" 20 by mmc.txt and the properties used by the sdhci-esdhc-imx driver. 25 - enum: 26 - fsl,imx25-esdhc 27 - fsl,imx35-esdhc [all …]
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/Linux-v6.1/Documentation/i2c/ |
D | slave-testunit-backend.rst | 1 .. SPDX-License-Identifier: GPL-2.0 7 by Wolfram Sang <wsa@sang-engineering.com> in 2020 11 easy to obtain). Examples include multi-master testing, and SMBus Host Notify 21 # echo "slave-testunit 0x1030" > /sys/bus/i2c/devices/i2c-0/new_device 23 After that, you will have a write-only device listening. Reads will just return 24 an 8-bit version number of the testunit. When writing, the device consists of 4 25 8-bit registers and, except for some "partial" commands, all registers must be 29 0x00 CMD - which test to trigger 30 0x01 DATAL - configuration byte 1 for the test 31 0x02 DATAH - configuration byte 2 for the test [all …]
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/Linux-v6.1/drivers/md/ |
D | dm-delay.c | 2 * Copyright (C) 2005-2007 Red Hat GmbH 16 #include <linux/device-mapper.h> 18 #define DM_MSG_PREFIX "delay" 23 unsigned delay; member 35 struct delay_class read; member 55 queue_work(dc->kdelayd_wq, &dc->flush_expired_bios); in handle_delayed_timer() 60 mutex_lock(&dc->timer_lock); in queue_timeout() 62 if (!timer_pending(&dc->delay_timer) || expires < dc->delay_timer.expires) in queue_timeout() 63 mod_timer(&dc->delay_timer, expires); in queue_timeout() 65 mutex_unlock(&dc->timer_lock); in queue_timeout() [all …]
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/Linux-v6.1/Documentation/devicetree/bindings/memory-controllers/ddr/ |
D | jedec,lpddr3-timings.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr3-timings.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: LPDDR3 SDRAM AC timing parameters for a given speed-bin 10 - Krzysztof Kozlowski <krzk@kernel.org> 14 const: jedec,lpddr3-timings 19 Maximum DDR clock frequency for the speed-bin, in Hz. 20 Property is deprecated, use max-freq. 23 max-freq: [all …]
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D | jedec,lpddr3.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr3.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: LPDDR3 SDRAM compliant to JEDEC JESD209-3 10 - Krzysztof Kozlowski <krzk@kernel.org> 15 - enum: 16 - samsung,K3QF2F20DB 17 - const: jedec,lpddr3 19 '#address-cells': [all …]
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/Linux-v6.1/drivers/net/wireless/ath/ath9k/ |
D | rng.c | 27 u32 v1, v2, rng_last = sc->rng_last; in ath9k_rng_data_read() 28 struct ath_hw *ah = sc->sc_ah; in ath9k_rng_data_read() 50 sc->rng_last = rng_last; in ath9k_rng_data_read() 57 u32 delay; in ath9k_rng_delay_get() local 60 delay = 10; in ath9k_rng_delay_get() 62 delay = 1000; in ath9k_rng_delay_get() 64 delay = 10000; in ath9k_rng_delay_get() 66 return delay; in ath9k_rng_delay_get() 91 bytes_read = -EIO; in ath9k_rng_read() 98 struct ath_hw *ah = sc->sc_ah; in ath9k_rng_start() [all …]
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/Linux-v6.1/Documentation/devicetree/bindings/spi/ |
D | cdns,qspi-nor-peripheral-props.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/spi/cdns,qspi-nor-peripheral-props.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Peripheral-specific properties for the Cadence QSPI controller. 10 See spi-peripheral-props.yaml for more info. 13 - Vaishnav Achath <vaishnav.a@ti.com> 16 # cdns,qspi-nor.yaml 17 cdns,read-delay: 20 Delay for read capture logic, in clock cycles. [all …]
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/Linux-v6.1/drivers/input/touchscreen/ |
D | wm9712.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later 3 * wm9712.c -- Codec driver for Wolfson WM9712 AC97 Codecs. 16 #include <linux/delay.h> 65 * Set adc sample delay. 71 * This delay can be set by setting delay = n, where n is the array 72 * position of the delay in the array delay_table below. 76 static int delay = 3; variable 77 module_param(delay, int, 0); 78 MODULE_PARM_DESC(delay, "Set adc sample delay."); 87 MODULE_PARM_DESC(five_wire, "Set to '1' to use 5-wire touchscreen."); [all …]
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D | wm9713.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later 3 * wm9713.c -- Codec touch driver for Wolfson WM9713 AC97 Codec. 16 #include <linux/delay.h> 65 * Set adc sample delay. 71 * This delay can be set by setting delay = n, where n is the array 72 * position of the delay in the array delay_table below. 76 static int delay = 4; variable 77 module_param(delay, int, 0); 78 MODULE_PARM_DESC(delay, "Set adc sample delay."); 87 MODULE_PARM_DESC(five_wire, "Set to '1' to use 5-wire touchscreen."); [all …]
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/Linux-v6.1/include/linux/reset/ |
D | reset-simple.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 9 * Maxime Ripard <maxime.ripard@free-electrons.com> 16 #include <linux/reset-controller.h> 20 * struct reset_simple_data - driver data for simple reset controllers 21 * @lock: spinlock to protect registers during read-modify-write cycles 27 * @status_active_low: if true, bits read back as cleared while the reset is 28 * asserted. Otherwise, bits read back as set while the 30 * @reset_us: Minimum delay in microseconds needed that needs to be 32 * device. If multiple consumers with different delay 34 * be the largest minimum delay. 0 means that such a delay is
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/Linux-v6.1/Documentation/hwmon/ |
D | nsa320.rst | 22 Adam Baker <linux@baker-net.org.uk> 25 ----------- 35 that contains 0x55 as a marker to indicate that data is being read correctly, 40 sysfs-Interface 41 --------------- 49 ----- 52 provided kernel. Testing has shown that if the delay between chip select and 56 read twice corrupting the output. The above analysis is based upon a sample 57 of one unit but suggests that the Zyxel provided delay values include a 62 time to read the data from the device and when it does it reads both temp and [all …]
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/Linux-v6.1/include/linux/platform_data/ |
D | gpmc-omap.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */ 5 * Copyright (C) 2014 Texas Instruments, Inc. - https://www.ti.com 34 /* Chip-select signal timings corresponding to GPMC_CS_CONFIG2 */ 36 u32 cs_rd_off; /* Read deassertion time */ 41 u32 adv_rd_off; /* Read deassertion time */ 44 u32 adv_aad_mux_rd_off; /* ADV read deassertion time for AAD */ 58 u32 page_burst_access; /* Multiple access word delay */ 59 u32 access; /* Start-cycle to first data valid delay */ 60 u32 rd_cycle; /* Total read cycle time */ 95 u32 t_rd_cycle; /* read cycle time */ [all …]
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/Linux-v6.1/arch/arm/boot/dts/ |
D | gemini-dlink-dns-313.dts | 1 // SPDX-License-Identifier: GPL-2.0 3 * Device Tree file for D-Link DNS-313 1-Bay Network Storage Enclosure 6 /dts-v1/; 9 #include <dt-bindings/input/input.h> 10 #include <dt-bindings/thermal/thermal.h> 13 model = "D-Link DNS-313 1-Bay Network Storage Enclosure"; 14 compatible = "dlink,dns-313", "cortina,gemini"; 15 #address-cells = <1>; 16 #size-cells = <1>; 19 /* 64 MB SDRAM in a Nanya NT5DS32M16BS-6K package */ [all …]
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/Linux-v6.1/arch/mips/sgi-ip22/ |
D | ip22-nvram.c | 1 // SPDX-License-Identifier: GPL-2.0 3 * ip22-nvram.c: NVRAM and serial EEPROM handling. 5 * Copyright (C) 2003 Ladislav Michl (ladis@linux-mips.org) 13 #define EEPROM_READ 0xc000 /* serial memory read */ 18 #define EEPROM_PRREAD 0xc000 /* read protect register */ 31 #define delay() ({ \ macro 39 delay(); \ 61 ser_cmd = cmd | (reg << (16 - BITS_IN_COMMAND)); in eeprom_cmd() 68 delay(); in eeprom_cmd() 70 delay(); in eeprom_cmd() [all …]
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/Linux-v6.1/samples/bpf/ |
D | ibumad_user.c | 1 // SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB 41 printf("failed to read key %u\n", key); in dump_counts() 51 printf("Read 'Class : count'\n"); in dump_all_counts() 62 bpf_link__destroy(tp_links[--tp_cnt]); in dump_exit() 70 {"delay", required_argument, NULL, 'd'}, 77 " --help, -h this menu\n" in usage() 78 " --delay, -d <delay> wait <delay> sec between prints [1 - 1000000]\n" in usage() 86 unsigned long delay = 5; in main() local 89 int opt, err = -1; in main() 92 long_options, &longindex)) != -1) { in main() [all …]
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/Linux-v6.1/drivers/scsi/qla4xxx/ |
D | ql4_83xx.c | 1 // SPDX-License-Identifier: GPL-2.0-only 4 * Copyright (c) 2003-2013 QLogic Corporation 17 return readl((void __iomem *)(ha->nx_pcibase + addr)); in qla4_83xx_rd_reg() 22 writel(val, (void __iomem *)(ha->nx_pcibase + addr)); in qla4_83xx_wr_reg() 30 qla4_83xx_wr_reg(ha, QLA83XX_CRB_WIN_FUNC(ha->func_num), addr); in qla4_83xx_set_win_base() 31 val = qla4_83xx_rd_reg(ha, QLA83XX_CRB_WIN_FUNC(ha->func_num)); in qla4_83xx_set_win_base() 33 ql4_printk(KERN_ERR, ha, "%s: Failed to set register window : addr written 0x%x, read 0x%x!\n", in qla4_83xx_set_win_base() 52 ql4_printk(KERN_ERR, ha, "%s: failed read of addr 0x%x!\n", in qla4_83xx_rd_reg_indirect() 91 __func__, ha->func_num, lock_owner); in qla4_83xx_flash_lock() 98 qla4_83xx_wr_reg(ha, QLA83XX_FLASH_LOCK_ID, ha->func_num); in qla4_83xx_flash_lock() [all …]
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/Linux-v6.1/include/uapi/linux/ |
D | taskstats.h | 1 /* SPDX-License-Identifier: LGPL-2.1 WITH Linux-syscall-note */ 2 /* taskstats.h - exporting per-task statistics 22 /* Format for per-task data returned to userland when 23 * - a task exits 24 * - listener requests stats for a task 33 * c) add new fields after version comment; maintain 64-bit alignment 57 /* Delay accounting fields start 59 * All values, until comment "Delay accounting fields end" are 60 * available only if delay accounting is enabled, even though the last 63 * xxx_count is the number of delay values recorded [all …]
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