Searched +full:rcar +full:- +full:gen2 +full:- +full:sata (Results 1 – 5 of 5) sorted by relevance
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)3 ---4 $id: "http://devicetree.org/schemas/ata/renesas,rcar-sata.yaml#"5 $schema: "http://devicetree.org/meta-schemas/core.yaml#"7 title: Renesas R-Car Serial-ATA Interface10 - Geert Uytterhoeven <geert+renesas@glider.be>15 - items:16 - enum:17 - renesas,sata-r8a7779 # R-Car H118 - items:[all …]
1 // SPDX-License-Identifier: GPL-2.03 * Device Tree Source for the R-Car M2-W (R8A77910) SoC5 * Copyright (C) 2013-2015 Renesas Electronics Corporation6 * Copyright (C) 2013-2014 Renesas Solutions Corp.10 #include <dt-bindings/clock/r8a7791-cpg-mssr.h>11 #include <dt-bindings/interrupt-controller/arm-gic.h>12 #include <dt-bindings/interrupt-controller/irq.h>13 #include <dt-bindings/power/r8a7791-sysc.h>17 #address-cells = <2>;18 #size-cells = <2>;[all …]
1 // SPDX-License-Identifier: GPL-2.08 #include <dt-bindings/clock/r8a7742-cpg-mssr.h>9 #include <dt-bindings/interrupt-controller/arm-gic.h>10 #include <dt-bindings/interrupt-controller/irq.h>11 #include <dt-bindings/power/r8a7742-sysc.h>15 #address-cells = <2>;16 #size-cells = <2>;24 compatible = "fixed-clock";25 #clock-cells = <0>;26 clock-frequency = <0>;[all …]
1 // SPDX-License-Identifier: GPL-2.03 * Device Tree Source for the R-Car H2 (R8A77900) SoC6 * Copyright (C) 2013-2014 Renesas Solutions Corp.10 #include <dt-bindings/clock/r8a7790-cpg-mssr.h>11 #include <dt-bindings/interrupt-controller/arm-gic.h>12 #include <dt-bindings/interrupt-controller/irq.h>13 #include <dt-bindings/power/r8a7790-sysc.h>17 #address-cells = <2>;18 #size-cells = <2>;46 compatible = "fixed-clock";[all …]
1 // SPDX-License-Identifier: GPL-2.0+3 * Renesas R-Car SATA driver6 * Copyright (C) 2013-2015 Cogent Embedded, Inc.7 * Copyright (C) 2013-2015 Renesas Solutions Corp.21 /* SH-Navi2G/ATAPI module compatible control registers */82 /* Serial-ATA HOST control registers */95 /* SATA INT status register (SATAINTSTAT) bits */99 /* SATA INT mask register (SATAINTSTAT) bits */121 /* Gen2 Physical Layer Control Registers */155 void __iomem *base = priv->base; in sata_rcar_gen1_phy_preinit()[all …]
