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/Linux-v5.10/Documentation/devicetree/bindings/reset/
Drenesas,rst.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: "http://devicetree.org/schemas/reset/renesas,rst.yaml#"
5 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
7 title: Renesas R-Car and RZ/G Reset Controller
10 - Geert Uytterhoeven <geert+renesas@glider.be>
11 - Magnus Damm <magnus.damm@gmail.com>
14 The R-Car and RZ/G Reset Controllers provide reset control, and implement the
16 - Latching of the levels on mode pins when PRESET# is negated,
17 - Mode monitoring register,
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/Linux-v5.10/drivers/soc/renesas/
Drcar-rst.c1 // SPDX-License-Identifier: GPL-2.0
3 * R-Car Gen1 RESET/WDT, R-Car Gen2, Gen3, and RZ/G RST Driver
11 #include <linux/soc/renesas/rcar-rst.h>
45 /* RZ/G1 is handled like R-Car Gen2 */
46 { .compatible = "renesas,r8a7742-rst", .data = &rcar_rst_gen2 },
47 { .compatible = "renesas,r8a7743-rst", .data = &rcar_rst_gen2 },
48 { .compatible = "renesas,r8a7744-rst", .data = &rcar_rst_gen2 },
49 { .compatible = "renesas,r8a7745-rst", .data = &rcar_rst_gen2 },
50 { .compatible = "renesas,r8a77470-rst", .data = &rcar_rst_gen2 },
51 /* RZ/G2 is handled like R-Car Gen3 */
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DMakefile1 # SPDX-License-Identifier: GPL-2.0
3 obj-$(CONFIG_SOC_RENESAS) += renesas-soc.o
6 obj-$(CONFIG_SYSC_R8A7742) += r8a7742-sysc.o
7 obj-$(CONFIG_SYSC_R8A7743) += r8a7743-sysc.o
8 obj-$(CONFIG_SYSC_R8A7745) += r8a7745-sysc.o
9 obj-$(CONFIG_SYSC_R8A77470) += r8a77470-sysc.o
10 obj-$(CONFIG_SYSC_R8A774A1) += r8a774a1-sysc.o
11 obj-$(CONFIG_SYSC_R8A774B1) += r8a774b1-sysc.o
12 obj-$(CONFIG_SYSC_R8A774C0) += r8a774c0-sysc.o
13 obj-$(CONFIG_SYSC_R8A774E1) += r8a774e1-sysc.o
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/Linux-v5.10/arch/arm64/boot/dts/renesas/
Dr8a77951.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the R-Car H3 (R8A77951) SoC
8 #include <dt-bindings/clock/r8a7795-cpg-mssr.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/power/r8a7795-sysc.h>
15 compatible = "renesas,r8a7795";
16 #address-cells = <2>;
17 #size-cells = <2>;
36 compatible = "fixed-clock";
37 #clock-cells = <0>;
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/Linux-v5.10/drivers/clk/renesas/
Dr8a7795-cpg-mssr.c1 // SPDX-License-Identifier: GPL-2.0
3 * r8a7795 Clock Pulse Generator / Module Standby and Software Reset
6 * Copyright (C) 2018-2019 Renesas Electronics Corp.
8 * Based on clk-rcar-gen3.c
16 #include <linux/soc/renesas/rcar-rst.h>
19 #include <dt-bindings/clock/r8a7795-cpg-mssr.h>
21 #include "renesas-cpg-mssr.h"
22 #include "rcar-gen3-cpg.h"
128 DEF_MOD("fdp1-2", 117, R8A7795_CLK_S2D1), /* ES1.x */
129 DEF_MOD("fdp1-1", 118, R8A7795_CLK_S0D1),
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Dr8a779a0-cpg-mssr.c1 // SPDX-License-Identifier: GPL-2.0
7 * Based on r8a7795-cpg-mssr.c
16 #include <linux/clk-provider.h>
24 #include <linux/soc/renesas/rcar-rst.h>
26 #include <dt-bindings/clock/r8a779a0-cpg-mssr.h>
28 #include "renesas-cpg-mssr.h"
29 #include "rcar-gen3-cpg.h"
166 parent = clks[core->parent & 0xffff]; /* some types use high bits */ in rcar_r8a779a0_cpg_clk_register()
170 switch (core->type) { in rcar_r8a779a0_cpg_clk_register()
172 div = cpg_pll_config->extal_div; in rcar_r8a779a0_cpg_clk_register()
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Dr8a77995-cpg-mssr.c1 // SPDX-License-Identifier: GPL-2.0
7 * Based on r8a7795-cpg-mssr.c
16 #include <linux/soc/renesas/rcar-rst.h>
18 #include <dt-bindings/clock/r8a77995-cpg-mssr.h>
20 #include "renesas-cpg-mssr.h"
21 #include "rcar-gen3-cpg.h"
123 DEF_MOD("sys-dmac2", 217, R8A77995_CLK_S3D1),
124 DEF_MOD("sys-dmac1", 218, R8A77995_CLK_S3D1),
125 DEF_MOD("sys-dmac0", 219, R8A77995_CLK_S3D1),
126 DEF_MOD("sceg-pub", 229, R8A77995_CLK_CR),
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Dr8a77980-cpg-mssr.c1 // SPDX-License-Identifier: GPL-2.0
8 * Based on r8a7795-cpg-mssr.c
16 #include <linux/soc/renesas/rcar-rst.h>
19 #include <dt-bindings/clock/r8a77980-cpg-mssr.h>
21 #include "renesas-cpg-mssr.h"
22 #include "rcar-gen3-cpg.h"
127 DEF_MOD("sys-dmac2", 217, R8A77980_CLK_S0D3),
128 DEF_MOD("sys-dmac1", 218, R8A77980_CLK_S0D3),
137 DEF_MOD("intc-ex", 407, R8A77980_CLK_CP),
138 DEF_MOD("intc-ap", 408, R8A77980_CLK_S0D3),
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Dr8a77970-cpg-mssr.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2017-2018 Cogent Embedded Inc.
7 * Based on r8a7795-cpg-mssr.c
12 #include <linux/clk-provider.h>
16 #include <linux/soc/renesas/rcar-rst.h>
18 #include <dt-bindings/clock/r8a77970-cpg-mssr.h>
20 #include "renesas-cpg-mssr.h"
21 #include "rcar-gen3-cpg.h"
125 DEF_MOD("sys-dmac2", 217, R8A77970_CLK_S2D1),
126 DEF_MOD("sys-dmac1", 218, R8A77970_CLK_S2D1),
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Dr8a77990-cpg-mssr.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2018-2019 Renesas Electronics Corp.
7 * Based on r8a7795-cpg-mssr.c
16 #include <linux/soc/renesas/rcar-rst.h>
18 #include <dt-bindings/clock/r8a77990-cpg-mssr.h>
20 #include "renesas-cpg-mssr.h"
21 #include "rcar-gen3-cpg.h"
136 DEF_MOD("sys-dmac2", 217, R8A77990_CLK_S3D1),
137 DEF_MOD("sys-dmac1", 218, R8A77990_CLK_S3D1),
138 DEF_MOD("sys-dmac0", 219, R8A77990_CLK_S3D1),
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Dr8a77965-cpg-mssr.c1 // SPDX-License-Identifier: GPL-2.0
8 * Based on r8a7795-cpg-mssr.c
17 #include <linux/soc/renesas/rcar-rst.h>
19 #include <dt-bindings/clock/r8a77965-cpg-mssr.h>
21 #include "renesas-cpg-mssr.h"
22 #include "rcar-gen3-cpg.h"
125 DEF_MOD("fdp1-0", 119, R8A77965_CLK_S0D1),
135 DEF_MOD("sys-dmac2", 217, R8A77965_CLK_S3D1),
136 DEF_MOD("sys-dmac1", 218, R8A77965_CLK_S3D1),
137 DEF_MOD("sys-dmac0", 219, R8A77965_CLK_S0D3),
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Dr8a7796-cpg-mssr.c1 // SPDX-License-Identifier: GPL-2.0
3 * r8a7796 (R-Car M3-W/W+) Clock Pulse Generator / Module Standby and Software
6 * Copyright (C) 2016-2019 Glider bvba
7 * Copyright (C) 2018-2019 Renesas Electronics Corp.
9 * Based on r8a7795-cpg-mssr.c
19 #include <linux/soc/renesas/rcar-rst.h>
21 #include <dt-bindings/clock/r8a7796-cpg-mssr.h>
23 #include "renesas-cpg-mssr.h"
24 #include "rcar-gen3-cpg.h"
130 DEF_MOD("fdp1-0", 119, R8A7796_CLK_S0D1),
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Dr8a774e1-cpg-mssr.c1 // SPDX-License-Identifier: GPL-2.0
7 * Based on r8a7795-cpg-mssr.c
15 #include <linux/soc/renesas/rcar-rst.h>
17 #include <dt-bindings/clock/r8a774e1-cpg-mssr.h>
19 #include "renesas-cpg-mssr.h"
20 #include "rcar-gen3-cpg.h"
124 DEF_MOD("fdp1-1", 118, R8A774E1_CLK_S0D1),
125 DEF_MOD("fdp1-0", 119, R8A774E1_CLK_S0D1),
142 DEF_MOD("sys-dmac2", 217, R8A774E1_CLK_S3D1),
143 DEF_MOD("sys-dmac1", 218, R8A774E1_CLK_S3D1),
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