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Searched +full:r8a7795 +full:- +full:lvds (Results 1 – 16 of 16) sorted by relevance

/Linux-v5.15/Documentation/devicetree/bindings/display/bridge/
Drenesas,lvds.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/bridge/renesas,lvds.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas R-Car LVDS Encoder
10 - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
13 These DT bindings describe the LVDS encoder embedded in the Renesas R-Car
14 Gen2, R-Car Gen3, RZ/G1 and RZ/G2 SoCs.
19 - renesas,r8a7742-lvds # for RZ/G1H compatible LVDS encoders
20 - renesas,r8a7743-lvds # for RZ/G1M compatible LVDS encoders
[all …]
/Linux-v5.15/drivers/gpu/drm/rcar-du/
Drcar_du_of_lvds_r8a7795.dts1 // SPDX-License-Identifier: GPL-2.0
3 * rcar_du_of_lvds_r8a7795.dts - Legacy LVDS DT bindings conversion for R8A7795
8 /dts-v1/;
12 #address-cells = <2>;
13 #size-cells = <2>;
15 lvds@feb90000 {
16 compatible = "renesas,r8a7795-lvds";
20 #address-cells = <1>;
21 #size-cells = <0>;
40 remote-endpoint = <&lvds0_input>;
Drcar_du_of.c1 // SPDX-License-Identifier: GPL-2.0
3 * rcar_du_of.c - Legacy DT bindings compatibility
23 /* -----------------------------------------------------------------------------
39 .compatible = "renesas,du-" #soc, \
59 return -ENODEV; in rcar_du_of_apply_overlay()
62 return of_overlay_fdt_apply(dtb->begin, dtb->end - dtb->begin, in rcar_du_of_apply_overlay()
72 int ret = -ENOMEM; in rcar_du_of_add_property()
76 return -ENOMEM; in rcar_du_of_add_property()
78 prop->name = kstrdup(name, GFP_KERNEL); in rcar_du_of_add_property()
79 if (!prop->name) in rcar_du_of_add_property()
[all …]
Drcar_du_drv.c1 // SPDX-License-Identifier: GPL-2.0+
3 * rcar_du_drv.c -- R-Car Display Unit DRM driver
5 * Copyright (C) 2013-2015 Renesas Electronics Corporation
33 /* -----------------------------------------------------------------------------
45 * R8A774[34] has one RGB output and one LVDS output
88 * R8A77470 has two RGB outputs, one LVDS output, and
115 * R8A774A1 has one RGB output, one LVDS output and one HDMI
144 * R8A774B1 has one RGB output, one LVDS output and one HDMI
171 * R8A774C0 has one RGB output and two LVDS outputs
199 * R8A774E1 has one RGB output, one LVDS output and one HDMI
[all …]
Drcar_lvds.c1 // SPDX-License-Identifier: GPL-2.0
3 * rcar_lvds.c -- R-Car LVDS Encoder
5 * Copyright (C) 2013-2018 Renesas Electronics Corporation
47 #define RCAR_LVDS_QUIRK_LANES BIT(0) /* LVDS lanes 1 and 3 inverted */
51 #define RCAR_LVDS_QUIRK_DUAL_LINK BIT(4) /* Supports dual-link operation */
56 void (*pll_setup)(struct rcar_lvds *lvds, unsigned int freq);
82 static void rcar_lvds_write(struct rcar_lvds *lvds, u32 reg, u32 data) in rcar_lvds_write() argument
84 iowrite32(data, lvds->mmio + reg); in rcar_lvds_write()
87 /* -----------------------------------------------------------------------------
91 static void rcar_lvds_pll_setup_gen2(struct rcar_lvds *lvds, unsigned int freq) in rcar_lvds_pll_setup_gen2() argument
[all …]
Drcar_du_crtc.c1 // SPDX-License-Identifier: GPL-2.0+
3 * rcar_du_crtc.c -- R-Car Display Unit CRTCs
5 * Copyright (C) 2013-2015 Renesas Electronics Corporation
37 struct rcar_du_device *rcdu = rcrtc->dev; in rcar_du_crtc_read()
39 return rcar_du_read(rcdu, rcrtc->mmio_offset + reg); in rcar_du_crtc_read()
44 struct rcar_du_device *rcdu = rcrtc->dev; in rcar_du_crtc_write()
46 rcar_du_write(rcdu, rcrtc->mmio_offset + reg, data); in rcar_du_crtc_write()
51 struct rcar_du_device *rcdu = rcrtc->dev; in rcar_du_crtc_clr()
53 rcar_du_write(rcdu, rcrtc->mmio_offset + reg, in rcar_du_crtc_clr()
54 rcar_du_read(rcdu, rcrtc->mmio_offset + reg) & ~clr); in rcar_du_crtc_clr()
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/Linux-v5.15/Documentation/devicetree/bindings/display/
Drenesas,du.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas R-Car Display Unit (DU)
10 - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
13 These DT bindings describe the Display Unit embedded in the Renesas R-Car
14 Gen1, R-Car Gen2, R-Car Gen3, RZ/G1 and RZ/G2 SoCs.
19 - renesas,du-r8a7742 # for RZ/G1H compatible DU
20 - renesas,du-r8a7743 # for RZ/G1M compatible DU
21 - renesas,du-r8a7744 # for RZ/G1N compatible DU
[all …]
/Linux-v5.15/arch/arm64/boot/dts/renesas/
Dr8a77951.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the R-Car H3 (R8A77951) SoC
8 #include <dt-bindings/clock/r8a7795-cpg-mssr.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/power/r8a7795-sysc.h>
20 compatible = "renesas,r8a7795";
21 #address-cells = <2>;
22 #size-cells = <2>;
41 compatible = "fixed-clock";
42 #clock-cells = <0>;
[all …]
/Linux-v5.15/drivers/clk/renesas/
Dr8a77980-cpg-mssr.c1 // SPDX-License-Identifier: GPL-2.0
8 * Based on r8a7795-cpg-mssr.c
16 #include <linux/soc/renesas/rcar-rst.h>
19 #include <dt-bindings/clock/r8a77980-cpg-mssr.h>
21 #include "renesas-cpg-mssr.h"
22 #include "rcar-gen3-cpg.h"
127 DEF_MOD("sys-dmac2", 217, R8A77980_CLK_S0D3),
128 DEF_MOD("sys-dmac1", 218, R8A77980_CLK_S0D3),
137 DEF_MOD("intc-ex", 407, R8A77980_CLK_CP),
138 DEF_MOD("intc-ap", 408, R8A77980_CLK_S0D3),
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Dr8a7795-cpg-mssr.c1 // SPDX-License-Identifier: GPL-2.0
3 * r8a7795 Clock Pulse Generator / Module Standby and Software Reset
6 * Copyright (C) 2018-2019 Renesas Electronics Corp.
8 * Based on clk-rcar-gen3.c
16 #include <linux/soc/renesas/rcar-rst.h>
19 #include <dt-bindings/clock/r8a7795-cpg-mssr.h>
21 #include "renesas-cpg-mssr.h"
22 #include "rcar-gen3-cpg.h"
128 DEF_MOD("fdp1-2", 117, R8A7795_CLK_S2D1), /* ES1.x */
129 DEF_MOD("fdp1-1", 118, R8A7795_CLK_S0D1),
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Dr8a77995-cpg-mssr.c1 // SPDX-License-Identifier: GPL-2.0
7 * Based on r8a7795-cpg-mssr.c
16 #include <linux/soc/renesas/rcar-rst.h>
18 #include <dt-bindings/clock/r8a77995-cpg-mssr.h>
20 #include "renesas-cpg-mssr.h"
21 #include "rcar-gen3-cpg.h"
129 DEF_MOD("sys-dmac2", 217, R8A77995_CLK_S3D1),
130 DEF_MOD("sys-dmac1", 218, R8A77995_CLK_S3D1),
131 DEF_MOD("sys-dmac0", 219, R8A77995_CLK_S3D1),
132 DEF_MOD("sceg-pub", 229, R8A77995_CLK_CR),
[all …]
Dr8a77970-cpg-mssr.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2017-2018 Cogent Embedded Inc.
7 * Based on r8a7795-cpg-mssr.c
12 #include <linux/clk-provider.h>
16 #include <linux/soc/renesas/rcar-rst.h>
18 #include <dt-bindings/clock/r8a77970-cpg-mssr.h>
20 #include "renesas-cpg-mssr.h"
21 #include "rcar-gen3-cpg.h"
125 DEF_MOD("sys-dmac2", 217, R8A77970_CLK_S2D1),
126 DEF_MOD("sys-dmac1", 218, R8A77970_CLK_S2D1),
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Dr8a77990-cpg-mssr.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2018-2019 Renesas Electronics Corp.
7 * Based on r8a7795-cpg-mssr.c
16 #include <linux/soc/renesas/rcar-rst.h>
18 #include <dt-bindings/clock/r8a77990-cpg-mssr.h>
20 #include "renesas-cpg-mssr.h"
21 #include "rcar-gen3-cpg.h"
141 DEF_MOD("sys-dmac2", 217, R8A77990_CLK_S3D1),
142 DEF_MOD("sys-dmac1", 218, R8A77990_CLK_S3D1),
143 DEF_MOD("sys-dmac0", 219, R8A77990_CLK_S3D1),
[all …]
Dr8a7796-cpg-mssr.c1 // SPDX-License-Identifier: GPL-2.0
3 * r8a7796 (R-Car M3-W/W+) Clock Pulse Generator / Module Standby and Software
6 * Copyright (C) 2016-2019 Glider bvba
7 * Copyright (C) 2018-2019 Renesas Electronics Corp.
9 * Based on r8a7795-cpg-mssr.c
19 #include <linux/soc/renesas/rcar-rst.h>
21 #include <dt-bindings/clock/r8a7796-cpg-mssr.h>
23 #include "renesas-cpg-mssr.h"
24 #include "rcar-gen3-cpg.h"
130 DEF_MOD("fdp1-0", 119, R8A7796_CLK_S0D1),
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Dr8a774e1-cpg-mssr.c1 // SPDX-License-Identifier: GPL-2.0
7 * Based on r8a7795-cpg-mssr.c
15 #include <linux/soc/renesas/rcar-rst.h>
17 #include <dt-bindings/clock/r8a774e1-cpg-mssr.h>
19 #include "renesas-cpg-mssr.h"
20 #include "rcar-gen3-cpg.h"
124 DEF_MOD("fdp1-1", 118, R8A774E1_CLK_S0D1),
125 DEF_MOD("fdp1-0", 119, R8A774E1_CLK_S0D1),
142 DEF_MOD("sys-dmac2", 217, R8A774E1_CLK_S3D1),
143 DEF_MOD("sys-dmac1", 218, R8A774E1_CLK_S3D1),
[all …]
Dr8a77965-cpg-mssr.c1 // SPDX-License-Identifier: GPL-2.0
8 * Based on r8a7795-cpg-mssr.c
17 #include <linux/soc/renesas/rcar-rst.h>
19 #include <dt-bindings/clock/r8a77965-cpg-mssr.h>
21 #include "renesas-cpg-mssr.h"
22 #include "rcar-gen3-cpg.h"
125 DEF_MOD("fdp1-0", 119, R8A77965_CLK_S0D1),
140 DEF_MOD("sys-dmac2", 217, R8A77965_CLK_S3D1),
141 DEF_MOD("sys-dmac1", 218, R8A77965_CLK_S3D1),
142 DEF_MOD("sys-dmac0", 219, R8A77965_CLK_S0D3),
[all …]