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/Linux-v6.1/arch/arm64/boot/dts/qcom/
Dqcs404-evb-1000.dts1 // SPDX-License-Identifier: GPL-2.0
4 /dts-v1/;
6 #include "qcs404-evb.dtsi"
9 model = "Qualcomm Technologies, Inc. QCS404 EVB 1000";
10 compatible = "qcom,qcs404-evb-1000", "qcom,qcs404-evb",
11 "qcom,qcs404";
DMakefile1 # SPDX-License-Identifier: GPL-2.0
2 dtb-$(CONFIG_ARCH_QCOM) += apq8016-sbc.dtb
3 dtb-$(CONFIG_ARCH_QCOM) += apq8094-sony-xperia-kitakami-karin_windy.dtb
4 dtb-$(CONFIG_ARCH_QCOM) += apq8096-db820c.dtb
5 dtb-$(CONFIG_ARCH_QCOM) += apq8096-ifc6640.dtb
6 dtb-$(CONFIG_ARCH_QCOM) += ipq6018-cp01-c1.dtb
7 dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk01.dtb
8 dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk10-c1.dtb
9 dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk10-c2.dtb
10 dtb-$(CONFIG_ARCH_QCOM) += msm8916-alcatel-idol347.dtb
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/Linux-v6.1/Documentation/devicetree/bindings/cpufreq/
Dqcom-cpufreq-nvmem.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/cpufreq/qcom-cpufreq-nvmem.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ilia Lin <ilia.lin@kernel.org>
13 In certain Qualcomm Technologies, Inc. SoCs such as QCS404, The CPU supply
25 - qcom,apq8064
26 - qcom,apq8096
27 - qcom,ipq8064
28 - qcom,msm8939
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/Linux-v6.1/Documentation/devicetree/bindings/arm/
Dqcom.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <bjorn.andersson@linaro.org>
18 Each board must specify a top-level board compatible string with the following
21 compatible = "qcom,<SoC>[-<soc_version>][-<foundry_id>]-<board>[/<subtype>][-<board_version>]"
42 qcs404
69 cp01-c1
72 hk10-c1
73 hk10-c2
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/Linux-v6.1/drivers/remoteproc/
Dqcom_q6v5_wcss.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2016-2018 Linaro Ltd.
5 * Copyright (c) 2012-2018, The Linux Foundation. All rights reserved.
161 val = readl(wcss->reg_base + Q6SS_RESET_REG); in q6v5_wcss_reset()
163 writel(val, wcss->reg_base + Q6SS_RESET_REG); in q6v5_wcss_reset()
166 val = readl(wcss->reg_base + Q6SS_XO_CBCR); in q6v5_wcss_reset()
168 writel(val, wcss->reg_base + Q6SS_XO_CBCR); in q6v5_wcss_reset()
171 ret = readl_poll_timeout(wcss->reg_base + Q6SS_XO_CBCR, in q6v5_wcss_reset()
175 dev_err(wcss->dev, in q6v5_wcss_reset()
180 val = readl(wcss->reg_base + Q6SS_PWR_CTL_REG); in q6v5_wcss_reset()
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