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/Linux-v6.1/Documentation/devicetree/bindings/pwm/
Dpwm.txt1 Specifying PWM information for devices
4 1) PWM user nodes
5 -----------------
7 PWM users should specify a list of PWM devices that they want to use
8 with a property containing a 'pwm-list':
10 pwm-list ::= <single-pwm> [pwm-list]
11 single-pwm ::= <pwm-phandle> <pwm-specifier>
12 pwm-phandle : phandle to PWM controller node
13 pwm-specifier : array of #pwm-cells specifying the given PWM
16 PWM properties should be named "pwms". The exact meaning of each pwms
[all …]
Dnvidia,tegra20-pwm.txt4 - compatible: Must be:
5 - "nvidia,tegra20-pwm": for Tegra20
6 - "nvidia,tegra30-pwm", "nvidia,tegra20-pwm": for Tegra30
7 - "nvidia,tegra114-pwm", "nvidia,tegra20-pwm": for Tegra114
8 - "nvidia,tegra124-pwm", "nvidia,tegra20-pwm": for Tegra124
9 - "nvidia,tegra132-pwm", "nvidia,tegra20-pwm": for Tegra132
10 - "nvidia,tegra210-pwm", "nvidia,tegra20-pwm": for Tegra210
11 - "nvidia,tegra186-pwm": for Tegra186
12 - "nvidia,tegra194-pwm": for Tegra194
13 - reg: physical base address and length of the controller's registers
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Dpwm-mediatek.txt1 MediaTek PWM controller
4 - compatible: should be "mediatek,<name>-pwm":
5 - "mediatek,mt2712-pwm": found on mt2712 SoC.
6 - "mediatek,mt6795-pwm": found on mt6795 SoC.
7 - "mediatek,mt7622-pwm": found on mt7622 SoC.
8 - "mediatek,mt7623-pwm": found on mt7623 SoC.
9 - "mediatek,mt7628-pwm": found on mt7628 SoC.
10 - "mediatek,mt7629-pwm": found on mt7629 SoC.
11 - "mediatek,mt8183-pwm": found on mt8183 SoC.
12 - "mediatek,mt8195-pwm", "mediatek,mt8183-pwm": found on mt8195 SoC.
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Dpwm-samsung.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/pwm/pwm-samsung.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung SoC PWM timers
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Krzysztof Kozlowski <krzk@kernel.org>
14 Samsung SoCs contain PWM timer blocks which can be used for system clock source
15 and clock event timers, as well as to drive SoC outputs with PWM signal. Each
16 PWM timer block provides 5 PWM channels (not all of them can drive physical
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Dpwm-fsl-ftm.txt1 Freescale FlexTimer Module (FTM) PWM controller
3 The same FTM PWM device can have a different endianness on different SoCs. The
6 for the endianness of the FTM PWM block as integrated into the existing SoCs:
8 SoC | FTM-PWM endianness
9 --------+-------------------
19 - compatible : should be "fsl,<soc>-ftm-pwm" and one of the following
21 - "fsl,vf610-ftm-pwm" for PWM compatible with the one integrated on VF610
22 - "fsl,imx8qm-ftm-pwm" for PWM compatible with the one integrated on i.MX8QM
23 - reg: Physical base address and length of the controller's registers
24 - #pwm-cells: Should be 3. See pwm.yaml in this directory for a description of
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Dallwinner,sun4i-a10-pwm.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/pwm/allwinner,sun4i-a10-pwm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner A10 PWM
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
14 "#pwm-cells":
19 - const: allwinner,sun4i-a10-pwm
20 - const: allwinner,sun5i-a10s-pwm
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Dpwm-st.txt1 STMicroelectronics PWM driver bindings
2 --------------------------------------
5 - compatible : "st,pwm"
6 - #pwm-cells : Number of cells used to specify a PWM. First cell
7 specifies the per-chip index of the PWM to use and the
8 second cell is the period in nanoseconds - fixed to 2
10 - reg : Physical base address and length of the controller's
12 - pinctrl-names: Set to "default".
13 - pinctrl-0: List of phandles pointing to pin configuration nodes
14 for PWM module.
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Datmel-hlcdc-pwm.txt1 Device-Tree bindings for Atmel's HLCDC (High-end LCD Controller) PWM driver
3 The Atmel HLCDC PWM is subdevice of the HLCDC MFD device.
4 See ../mfd/atmel-hlcdc.txt for more details.
7 - compatible: value should be one of the following:
8 "atmel,hlcdc-pwm"
9 - pinctr-names: the pin control state names. Should contain "default".
10 - pinctrl-0: should contain the pinctrl states described by pinctrl
12 - #pwm-cells: should be set to 3. This PWM chip use the default 3 cells
13 bindings defined in pwm.yaml in this directory.
18 compatible = "atmel,sama5d3-hlcdc";
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Dimx-pwm.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pwm/imx-pwm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale i.MX PWM controller
10 - Philipp Zabel <p.zabel@pengutronix.de>
13 - $ref: pwm.yaml#
16 "#pwm-cells":
18 Should be 2 for i.MX1 and 3 for i.MX27 and newer SoCs. See pwm.yaml
21 - 2
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Dimg-pwm.txt1 *Imagination Technologies PWM DAC driver
4 - compatible: Should be "img,pistachio-pwm"
5 - reg: Should contain physical base address and length of pwm registers.
6 - clocks: Must contain an entry for each entry in clock-names.
7 See ../clock/clock-bindings.txt for details.
8 - clock-names: Must include the following entries.
9 - pwm: PWM operating clock.
10 - sys: PWM system interface clock.
11 - #pwm-cells: Should be 2. See pwm.yaml in this directory for the
13 - img,cr-periph: Must contain a phandle to the peripheral control
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Dpwm-meson.txt1 Amlogic Meson PWM Controller
5 - compatible: Shall contain "amlogic,meson8b-pwm"
6 or "amlogic,meson-gxbb-pwm"
7 or "amlogic,meson-gxbb-ao-pwm"
8 or "amlogic,meson-axg-ee-pwm"
9 or "amlogic,meson-axg-ao-pwm"
10 or "amlogic,meson-g12a-ee-pwm"
11 or "amlogic,meson-g12a-ao-pwm-ab"
12 or "amlogic,meson-g12a-ao-pwm-cd"
13 - #pwm-cells: Should be 3. See pwm.yaml in this directory for a description of
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Dpwm-rockchip.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/pwm/pwm-rockchip.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip PWM controller
10 - Heiko Stuebner <heiko@sntech.de>
15 - const: rockchip,rk2928-pwm
16 - const: rockchip,rk3288-pwm
17 - const: rockchip,rk3328-pwm
18 - const: rockchip,vop-pwm
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Dlpc1850-sct-pwm.txt1 * NXP LPC18xx State Configurable Timer - Pulse Width Modulator driver
4 - compatible: Should be "nxp,lpc1850-sct-pwm"
5 - reg: Should contain physical base address and length of pwm registers.
6 - clocks: Must contain an entry for each entry in clock-names.
7 See ../clock/clock-bindings.txt for details.
8 - clock-names: Must include the following entries.
9 - pwm: PWM operating clock.
10 - #pwm-cells: Should be 3. See pwm.yaml in this directory for the description
14 pwm: pwm@40000000 {
15 compatible = "nxp,lpc1850-sct-pwm";
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Dmediatek,pwm-disp.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pwm/mediatek,pwm-disp.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jitao Shi <jitao.shi@mediatek.com>
11 - Xinlei Lee <xinlei.lee@mediatek.com>
14 - $ref: pwm.yaml#
19 - enum:
20 - mediatek,mt2701-disp-pwm
21 - mediatek,mt6595-disp-pwm
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/Linux-v6.1/Documentation/devicetree/bindings/clock/
Dnvidia,tegra124-dfll.txt4 Documentation/devicetree/bindings/clock/clock-bindings.txt
7 the fast CPU cluster. It consists of a free-running voltage controlled
10 communicating with an off-chip PMIC either via an I2C bus or via PWM signals.
13 - compatible : should be one of:
14 - "nvidia,tegra124-dfll": for Tegra124
15 - "nvidia,tegra210-dfll": for Tegra210
16 - reg : Defines the following set of registers, in the order listed:
17 - registers for the DFLL control logic.
18 - registers for the I2C output logic.
19 - registers for the integrated I2C master controller.
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/Linux-v6.1/arch/arm64/boot/dts/rockchip/
Drk356x.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/rk3568-cru.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/phy/phy.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/power/rk3568-power.h>
12 #include <dt-bindings/soc/rockchip,boot-mode.h>
13 #include <dt-bindings/thermal/thermal.h>
16 interrupt-parent = <&gic>;
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Drk3308.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include <dt-bindings/clock/rk3308-cru.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/pinctrl/rockchip.h>
12 #include <dt-bindings/soc/rockchip,boot-mode.h>
13 #include <dt-bindings/thermal/thermal.h>
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
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/Linux-v6.1/Documentation/devicetree/bindings/timer/
Dingenic,tcu.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 Documentation/mips/ingenic-tcu.rst.
14 - Paul Cercueil <paul@crapouillou.net>
21 - ingenic,jz4740-tcu
22 - ingenic,jz4725b-tcu
23 - ingenic,jz4760-tcu
24 - ingenic,jz4760b-tcu
25 - ingenic,jz4770-tcu
[all …]
/Linux-v6.1/arch/arm/boot/dts/
Drv1108.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 #include <dt-bindings/gpio/gpio.h>
4 #include <dt-bindings/interrupt-controller/irq.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/clock/rv1108-cru.h>
7 #include <dt-bindings/pinctrl/rockchip.h>
8 #include <dt-bindings/thermal/thermal.h>
10 #address-cells = <1>;
11 #size-cells = <1>;
15 interrupt-parent = <&gic>;
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Dstm32f429.dtsi2 * Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com>
4 * This file is dual-licensed: you can use it either under the terms
22 * MA 02110-1301 USA
48 #include "armv7-m.dtsi"
49 #include <dt-bindings/clock/stm32fx-clock.h>
50 #include <dt-bindings/mfd/stm32f4-rcc.h>
53 #address-cells = <1>;
54 #size-cells = <1>;
57 clk_hse: clk-hse {
58 #clock-cells = <0>;
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Dstm32f746.dtsi2 * Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com>
4 * This file is dual-licensed: you can use it either under the terms
43 #include "armv7-m.dtsi"
44 #include <dt-bindings/clock/stm32fx-clock.h>
45 #include <dt-bindings/mfd/stm32f7-rcc.h>
48 #address-cells = <1>;
49 #size-cells = <1>;
52 clk_hse: clk-hse {
53 #clock-cells = <0>;
54 compatible = "fixed-clock";
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Dstm32mp151.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/stm32mp1-clks.h>
8 #include <dt-bindings/reset/stm32mp1-resets.h>
11 #address-cells = <1>;
12 #size-cells = <1>;
15 #address-cells = <1>;
16 #size-cells = <0>;
19 compatible = "arm,cortex-a7";
[all …]
/Linux-v6.1/Documentation/devicetree/bindings/hwmon/
Dnpcm750-pwm-fan.txt1 Nuvoton NPCM7xx PWM and Fan Tacho controller device
3 The Nuvoton BMC NPCM7XX supports 8 Pulse-width modulation (PWM)
6 Required properties for pwm-fan node
7 - #address-cells : should be 1.
8 - #size-cells : should be 0.
9 - compatible : "nuvoton,npcm750-pwm-fan" for Poleg NPCM7XX.
10 - reg : specifies physical base address and size of the registers.
11 - reg-names : must contain:
12 * "pwm" for the PWM registers.
14 - clocks : phandle of reference clocks.
[all …]
/Linux-v6.1/Documentation/devicetree/bindings/soc/microchip/
Datmel,at91rm9200-tcb.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/microchip/atmel,at91rm9200-tcb.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Alexandre Belloni <alexandre.belloni@bootlin.com>
19 - enum:
20 - atmel,at91rm9200-tcb
21 - atmel,at91sam9x5-tcb
22 - atmel,sama5d2-tcb
23 - const: simple-mfd
[all …]
/Linux-v6.1/Documentation/devicetree/bindings/mfd/
Dst,stm32-timers.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mfd/st,stm32-timers.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 This hardware block provides 3 types of timer along with PWM functionality:
11 - advanced-control timers consist of a 16-bit auto-reload counter driven
12 by a programmable prescaler, break input feature, PWM outputs and
13 complementary PWM outputs channels.
14 - general-purpose timers consist of a 16-bit or 32-bit auto-reload counter
15 driven by a programmable prescaler and PWM outputs.
[all …]

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