| /Linux-v6.6/Documentation/ABI/testing/ |
| D | sysfs-class-remoteproc | 4 Description: Remote processor firmware
7 remote processor.
9 To change the running firmware, ensure the remote processor is
15 Description: Remote processor state
17 Reports the state of the remote processor, which will be one of:
25 "offline" means the remote processor is powered off.
27 "suspended" means that the remote processor is suspended and
30 "running" is the normal state of an available remote processor
33 the remote processor.
35 "invalid" is returned if the remote processor is in an
[all …]
|
| /Linux-v6.6/arch/sh/ |
| D | Kconfig | 78 The SuperH is a RISC processor targeted for use in embedded systems
152 # Processor families
214 prompt "Processor sub-type selection"
217 # Processor subtypes
220 # SH-2 Processor Support
223 bool "Support SH7619 processor"
228 bool "Support J2 processor"
233 # SH-2A Processor Support
236 bool "Support SH7201 processor"
242 bool "Support SH7203 processor"
[all …]
|
| /Linux-v6.6/tools/perf/pmu-events/arch/powerpc/power8/ |
| D | cache.json | 5 …"BriefDescription": "The processor's data cache was reloaded with Modified (M) data from another c…
6 …"PublicDescription": "The processor's data cache was reloaded with Modified (M) data from another …
11 …"BriefDescription": "The processor's data cache was reloaded with Shared (S) data from another chi…
12 …"PublicDescription": "The processor's data cache was reloaded with Shared (S) data from another ch…
17 …"BriefDescription": "The processor's data cache was reloaded from another chip's L4 on a different…
18 …"PublicDescription": "The processor's data cache was reloaded from another chip's L4 on a differen…
23 …"BriefDescription": "The processor's data cache was reloaded from local core's L2 due to a demand …
24 …"PublicDescription": "The processor's data cache was reloaded from local core's L2 due to either o…
35 …"BriefDescription": "The processor's data cache was reloaded from a location other than the local …
36 …"PublicDescription": "The processor's data cache was reloaded from a location other than the local…
[all …]
|
| D | frontend.json | 89 …"BriefDescription": "The processor's Instruction cache was reloaded with Modified (M) data from an…
90 …"PublicDescription": "The processor's Instruction cache was reloaded with Modified (M) data from a…
95 …"BriefDescription": "The processor's Instruction cache was reloaded with Shared (S) data from anot…
96 …"PublicDescription": "The processor's Instruction cache was reloaded with Shared (S) data from ano…
101 …"BriefDescription": "The processor's Instruction cache was reloaded from another chip's L4 on a di…
102 …"PublicDescription": "The processor's Instruction cache was reloaded from another chip's L4 on a d…
107 …"BriefDescription": "The processor's Instruction cache was reloaded from another chip's memory on …
108 …"PublicDescription": "The processor's Instruction cache was reloaded from another chip's memory on…
113 …"BriefDescription": "The processor's Instruction cache was reloaded from local core's L2 due to an…
114 …"PublicDescription": "The processor's Instruction cache was reloaded from local core's L2 due to e…
[all …]
|
| D | other.json | 371 …"BriefDescription": "The processor's data cache was reloaded with Modified (M) data from another c…
372 …"PublicDescription": "The processor's data cache was reloaded with Modified (M) data from another …
377 …"BriefDescription": "The processor's data cache was reloaded with Shared (S) data from another chi…
378 …"PublicDescription": "The processor's data cache was reloaded with Shared (S) data from another ch…
383 …"BriefDescription": "The processor's data cache was reloaded from another chip's L4 on a different…
384 …"PublicDescription": "The processor's data cache was reloaded from another chip's L4 on a differen…
389 …"BriefDescription": "The processor's data cache was reloaded from another chip's memory on the sam…
390 …"PublicDescription": "The processor's data cache was reloaded from another chip's memory on the sa…
395 …"BriefDescription": "The processor's data cache was reloaded from local core's L2 due to either de…
396 …"PublicDescription": "The processor's data cache was reloaded from local core's L2 due to either o…
[all …]
|
| /Linux-v6.6/drivers/eisa/ |
| D | eisa.ids | 74 AIR1001 "AIR P6NDP PCI/EISA Dual-Pentium Processor System Board"
84 ALR3000 "80486 Processor Module"
85 ALR3010 "Pentium Processor Board"
91 ALRB0A0 "Primary System Processor Board - 80486DX2/66"
92 ALRB0B0 "Secondary System Processor Board - 80486DX2/66"
245 CPQ5000 "Compaq 386/33 System Processor Board used as Secondary"
246 CPQ5251 "Compaq 5/133 System Processor Board-2MB"
247 CPQ5253 "Compaq 5/166 System Processor Board-2MB"
248 CPQ5255 "Compaq 5/133 System Processor Board-1MB"
249 CPQ525D "Compaq 5/100 System Processor Board-1MB"
[all …]
|
| /Linux-v6.6/arch/arm/mach-imx/ |
| D | Kconfig | 47 This enables support for Freescale i.MX31 processor
54 This enables support for Freescale i.MX35 processor
66 This enables support for Freescale i.MX1 processor
78 This enables support for Freescale i.MX25 processor
86 This enables support for Freescale i.MX27 processor
105 This enables support for Freescale i.MX50 processor.
112 This enables support for Freescale i.MX51 processor
120 This enables support for Freescale i.MX53 processor.
144 This enables support for Freescale i.MX6 Quad processor.
154 This enables support for Freescale i.MX6 SoloLite processor.
[all …]
|
| /Linux-v6.6/drivers/net/phy/mscc/ |
| D | mscc_ptp.c | 23 /* Two PHYs share the same 1588 processor and it's to be entirely configured
24 * through the base PHY of this processor.
59 PROCESSOR, enumerator
77 case PROCESSOR: in vsc85xx_ts_read_csr()
117 blk == PROCESSOR; in vsc85xx_ts_write_csr()
127 case PROCESSOR: in vsc85xx_ts_write_csr()
254 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_EGR_STALL_LATENCY, in vsc85xx_ts_set_latencies()
274 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_INGR_LOCAL_LATENCY, in vsc85xx_ts_set_latencies()
277 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, in vsc85xx_ts_set_latencies()
280 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_INGR_TSP_CTRL, in vsc85xx_ts_set_latencies()
[all …]
|
| /Linux-v6.6/arch/m68k/ |
| D | Kconfig.cpu | 2 comment "Processor Type"
10 the full 68000 processor instruction set.
12 of the 68000 processor family. They are mainly targeted at embedded
15 processor instruction set.
17 MC68xxx processor, select M68KCLASSIC.
19 processor, select COLDFIRE.
63 processor, say Y. Otherwise, say N. Note that the 68020 requires a
74 processor, say Y. Otherwise, say N. Note that a MC68EC030 will not
84 or MC68040 processor, say Y. Otherwise, say N. Note that an
95 processor, say Y. Otherwise, say N.
[all …]
|
| /Linux-v6.6/Documentation/powerpc/ |
| D | elf_hwcaps.rst | 80 The processor is PowerPC 601.
93 The processor is 40x or 44x family.
96 The processor has a unified L1 cache for instructions and data, as
98 Unused in the kernel since 39c8bf2b3cc1 ("powerpc: Retire e200 core (mpc555x processor)")
111 This is a 601 specific HWCAP, so if it is known that the processor
117 The processor is POWER4 or PPC970/FX/MP.
121 The processor is POWER5.
124 The processor is POWER5+.
127 The processor is Cell.
130 The processor implements the embedded category ("BookE") architecture.
[all …]
|
| /Linux-v6.6/Documentation/admin-guide/pm/ |
| D | intel_idle.rst | 20 a particular processor model in it depends on whether or not it recognizes that
21 processor model and may also depend on information coming from the platform
26 ``intel_idle`` uses the ``MWAIT`` instruction to inform the processor that the
28 processor's functional blocks into low-power states. That instruction takes two
30 first of which, referred to as a *hint*, can be used by the processor to
47 Each ``MWAIT`` hint value is interpreted by the processor as a license to
48 reconfigure itself in a certain way in order to save energy. The processor
52 processor) corresponding to them depends on the processor model and it may also
59 for different processor models included in the driver itself and the ACPI tables
60 of the system. The former are always used if the processor model at hand is
[all …]
|
| /Linux-v6.6/drivers/remoteproc/ |
| D | Kconfig | 5 bool "Support for Remote Processor subsystem"
33 processor framework.
44 processor framework.
62 Say y here to support Mediatek's System Companion Processor (SCP) via
63 the remote processor framework.
75 and DSP on OMAP4) via the remote processor framework.
102 Say y here to support Wakeup M3 remote processor on TI AM33xx
116 remote processor framework.
136 via the remote processor framework.
142 tristate "Amlogic Meson6/8/8b/8m2 AO ARC remote processor support"
[all …]
|
| /Linux-v6.6/Documentation/devicetree/bindings/interrupt-controller/ |
| D | fsl,mu-msi.yaml | 16 for one processor (A side) to signal the other processor (B side) using
23 registers (Processor A-side, Processor B-side).
45 - const: processor-a-side
46 - const: processor-b-side
62 - const: processor-a-side
63 - const: processor-b-side
94 reg-names = "processor-a-side", "processor-b-side";
98 power-domain-names = "processor-a-side", "processor-b-side";
|
| /Linux-v6.6/Documentation/devicetree/bindings/remoteproc/ |
| D | ti,omap-remoteproc.yaml | 13 The OMAP family of SoCs usually have one or more slave processor sub-systems
14 that are used to offload some of the processor-intensive tasks, or to manage
17 The processor cores in the sub-system are usually behind an IOMMU, and may
21 The OMAP SoCs usually have a DSP processor sub-system and/or an IPU processor
22 sub-system. The DSP processor sub-system can contain any of the TI's C64x,
23 C66x or C67x family of DSP cores as the main execution unit. The IPU processor
27 Each remote processor sub-system is represented as a single DT node. Each node
29 the host processor (MPU) to perform the device management of the remote
30 processor and to communicate with the remote processor. The various properties
54 for this remote processor to access any external RAM memory or
[all …]
|
| D | xlnx,zynqmp-r5fss.yaml | 7 title: Xilinx R5F processor subsystem
15 real-time processing based on the Cortex-R5F processor core from ARM.
16 The Cortex-R5F processor implements the Arm v7-R architecture and includes a
27 The RPU MPCore can operate in split mode (Dual-processor performance), Safety
30 core 1 runs normally). The processor does not support dynamic configuration.
31 Switching between modes is only permitted immediately after a processor reset.
43 The RPU is located in the Low Power Domain of the Processor Subsystem.
44 Each processor includes separate L1 instruction and data caches and
50 per processor. In lock-step mode, the processor has access to 256KB of
91 the remote processor (e.g. remoteproc firmware and carveouts, rpmsg
|
| /Linux-v6.6/Documentation/devicetree/bindings/soc/qcom/ |
| D | qcom,smsm.yaml | 16 information between the processors in a Qualcomm SoC. Each processor is
17 assigned 32 bits of state that can be modified. A processor can through a
19 certain bit owned by a certain remote processor.
32 Identifier of the local processor in the list of hosts, or in other words
34 processor.
49 remote processor.
54 Each processor's state bits are described by a subnode of the SMSM device
56 remote processor's state bits or the local processors bits. The node
66 belong to a remote processor.
74 One entry specifying remote IRQ used by the remote processor to
[all …]
|
| /Linux-v6.6/arch/arm/include/asm/ |
| D | proc-fns.h | 23 struct processor { struct
33 * Set up any processor specifics argument
37 * Check for processor bugs argument
41 * Disable any processor specifics argument
49 * Idle the processor argument
53 * Processor architecture specific
82 static inline void init_proc_vtable(const struct processor *p) in init_proc_vtable() argument
103 extern struct processor processor;
113 extern struct processor *cpu_vtable[];
116 static inline void init_proc_vtable(const struct processor *p) in init_proc_vtable()
[all …]
|
| /Linux-v6.6/tools/perf/pmu-events/arch/x86/goldmont/ |
| D | cache.json | 64 …processor) in the system, one of those caching agents indicated that they had a dirty copy of the …
216 …demand & prefetch) that miss the L2 cache with a snoop hit in the other processor module, data for…
221 …demand & prefetch) that miss the L2 cache with a snoop hit in the other processor module, data for…
226 …demand & prefetch) that miss the L2 cache with a snoop hit in the other processor module, no data …
231 …demand & prefetch) that miss the L2 cache with a snoop hit in the other processor module, no data …
236 …mand & prefetch) that true miss for the L2 cache with a snoop miss in the other processor module.",
241 …refetch) that true miss for the L2 cache with a snoop miss in the other processor module. Require…
266 … or L2 prefetchers that miss the L2 cache with a snoop hit in the other processor module, data for…
271 … or L2 prefetchers that miss the L2 cache with a snoop hit in the other processor module, data for…
276 … or L2 prefetchers that miss the L2 cache with a snoop hit in the other processor module, no data …
[all …]
|
| /Linux-v6.6/arch/ia64/include/asm/ |
| D | pal.h | 6 * Processor Abstraction Layer definitions.
9 * chapter 11 IA-64 Processor Abstraction Layer
21 * 00/03/23 cfleck Modified processor min-state save area to match updated PAL & SAL info
42 #define PAL_BUS_GET_FEATURES 9 /* return processor bus interface features settings */
43 #define PAL_BUS_SET_FEATURES 10 /* set processor bus features */
47 #define PAL_FREQ_RATIOS 14 /* ratio of processor, bus and ITC frequency */
49 #define PAL_PLATFORM_ADDR 16 /* set processor interrupt block and IO port space addr */
50 #define PAL_PROC_GET_FEATURES 17 /* get configurable processor features & settings */
51 #define PAL_PROC_SET_FEATURES 18 /* enable/disable configurable processor features */
54 #define PAL_MC_CLEAR_LOG 21 /* clear all processor log info */
[all …]
|
| /Linux-v6.6/tools/perf/pmu-events/arch/x86/amdzen4/ |
| D | data-fabric.json | 4 … "PublicDescription": "Read data beats (64 bytes) for local processor at Coherent Station (CS) 0.",
12 … "PublicDescription": "Read data beats (64 bytes) for local processor at Coherent Station (CS) 1.",
20 … "PublicDescription": "Read data beats (64 bytes) for local processor at Coherent Station (CS) 2.",
28 … "PublicDescription": "Read data beats (64 bytes) for local processor at Coherent Station (CS) 3.",
36 … "PublicDescription": "Read data beats (64 bytes) for local processor at Coherent Station (CS) 4.",
44 … "PublicDescription": "Read data beats (64 bytes) for local processor at Coherent Station (CS) 5.",
52 … "PublicDescription": "Read data beats (64 bytes) for local processor at Coherent Station (CS) 6.",
60 … "PublicDescription": "Read data beats (64 bytes) for local processor at Coherent Station (CS) 7.",
68 … "PublicDescription": "Read data beats (64 bytes) for local processor at Coherent Station (CS) 8.",
76 … "PublicDescription": "Read data beats (64 bytes) for local processor at Coherent Station (CS) 9.",
[all …]
|
| /Linux-v6.6/tools/power/cpupower/man/ |
| D | cpupower-monitor.1 | 3 cpupower\-monitor \- Report processor frequency and idle statistics
18 \fBcpupower-monitor \fP reports processor topology, frequency and idle power
22 \fBcpupower-monitor \fP implements independent processor sleep state and
42 The name and a description of each counter and its processor hierarchy level
50 [P] \-> Processor Package (Socket)
106 state it is also used to show C0 (processor is active) and Cx (processor is in
122 For example an IvyBridge processor has sleep state capabilities which got
123 introduced in Nehalem and SandyBridge processor families.
124 Thus on an IvyBridge processor one will get Nehalem and SandyBridge sleep
130 AMD laptop and desktop processor (family 12h and 14h) sleep state counters.
[all …]
|
| /Linux-v6.6/Documentation/staging/ |
| D | rpmsg.rst | 2 Remote Processor Messaging (rpmsg) Framework
14 Modern SoCs typically employ heterogeneous remote processor devices in
26 multimedia tasks from the main application processor.
34 hardware accessible only by the remote processor, reserving kernel-controlled
35 resources on behalf of the remote processor, etc..).
48 to the processor. To minimize the risks of rogue (or buggy) userland code
54 Every rpmsg device is a communication channel with a remote processor (thus
73 sends a message across to the remote processor on a given channel.
80 one becomes available (i.e. until the remote processor consumes
92 sends a message across to the remote processor on a given channel,
[all …]
|
| D | remoteproc.rst | 2 Remote Processor Framework
8 Modern SoCs typically have heterogeneous remote processor devices in asymmetric
29 existing virtio drivers with remote processor backends at a minimal development
39 Boot a remote processor (i.e. load its firmware, power it on, ...).
41 If the remote processor is already powered on, this function immediately
54 Power off a remote processor (previously booted with rproc_boot()).
76 the remote processor's refcount, so always use rproc_put() to
91 /* let's power on and boot our remote processor */
100 * our remote processor is now powered on... give it some work
116 Allocate a new remote processor handle, but don't register
[all …]
|
| /Linux-v6.6/Documentation/core-api/ |
| D | this_cpu_ops.rst | 9 variables associated with the *currently* executing processor. This is
12 specific processor).
14 this_cpu operations add a per cpu variable offset to the processor
21 processor is not changed between the calculation of the address and
33 data specific to the currently executing processor. Only the current
34 processor should be accessing that variable and therefore there are no
70 the processor. So the relocation to the per cpu base is encoded in the
87 prevent the kernel from moving the thread to a different processor
110 reserved for a specific processor. Without disabling preemption in the
115 the value of the individual counters for each processor are
[all …]
|
| /Linux-v6.6/drivers/acpi/ |
| D | acpi_processor.c | 3 * acpi_processor.c - ACPI processor enumeration support
23 #include <acpi/processor.h>
168 /* Check presence of Processor Clocking Control by searching for \_SB.PCCH. */
274 /* Declared with "Processor" statement; match ProcessorID */ in acpi_processor_get_info()
278 "Failed to evaluate processor object (0x%x)\n", in acpi_processor_get_info()
283 pr->acpi_id = object.processor.proc_id; in acpi_processor_get_info()
292 "Failed to evaluate processor _UID (0x%x)\n", in acpi_processor_get_info()
306 "Failed to get unique processor _UID (0x%x)\n", in acpi_processor_get_info()
327 * Check availability of Processor Performance Control by in acpi_processor_get_info()
329 * processor definition. in acpi_processor_get_info()
[all …]
|
