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/Linux-v5.15/Documentation/userspace-api/media/v4l/
Dext-ctrls-fm-tx.rst1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _fm-tx-controls:
15 .. _fm-tx-control-id:
27 step are driver-specific.
34 to 31 pre-defined programme types.
52 programme-related information or any other text. In these cases,
103 receiver-generated distortion and prevent overmodulation.
107 useconds. Step and range are driver-specific.
111 are driver-specific.
121 range and step are driver-specific.
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Dext-ctrls-fm-rx.rst1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _fm-rx-controls:
13 .. _fm-rx-control-id:
27 Gets RDS Programme Type field. This encodes up to 31 pre-defined
45 wishes to transmit longer PS names, programme-related information or
70 enum v4l2_deemphasis -
71 Configures the de-emphasis value for reception. A de-emphasis filter
75 values for de-emphasis. Here they are:
79 .. flat-table::
80 :header-rows: 0
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/Linux-v5.15/Documentation/devicetree/bindings/phy/
Dapm-xgene-phy.txt1 * APM X-Gene 15Gbps Multi-purpose PHY nodes
3 PHY nodes are defined to describe on-chip 15Gbps Multi-purpose PHY. Each
7 - compatible : Shall be "apm,xgene-phy".
8 - reg : PHY memory resource is the SDS PHY access resource.
9 - #phy-cells : Shall be 1 as it expects one argument for setting
14 - status : Shall be "ok" if enabled or "disabled" if disabled.
16 - clocks : Reference to the clock entry.
17 - apm,tx-eye-tuning : Manual control to fine tune the capture of the serial
19 Two set of 3-tuple setting for each (up to 3)
22 - apm,tx-eye-direction : Eye tuning manual control direction. 0 means sample
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Dqcom,qusb2-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: "http://devicetree.org/schemas/phy/qcom,qusb2-phy.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
11 - Manu Gautam <mgautam@codeaurora.org>
19 - items:
20 - enum:
21 - qcom,ipq8074-qusb2-phy
22 - qcom,msm8996-qusb2-phy
23 - qcom,msm8998-qusb2-phy
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/Linux-v5.15/include/linux/phy/
Dphy-dp.h1 /* SPDX-License-Identifier: GPL-2.0 */
12 * struct phy_configure_opts_dp - DisplayPort PHY configuration set
49 * @pre:
51 * Pre-emphasis levels, as specified by DisplayPort specification, to be
56 unsigned int pre[4]; member
61 * Flag indicating, whether or not to enable spread-spectrum clocking.
88 * and pre-emphasis to requested values. Only lanes specified
/Linux-v5.15/drivers/gpu/drm/sti/
Dsti_hdmi_tx3g4c28phy.c1 // SPDX-License-Identifier: GPL-2.0
70 * sti_hdmi_tx3g4c28phy_start - Start hdmi phy macro cell tx3g4c28
78 u32 ckpxpll = hdmi->mode.clock * 1000; in sti_hdmi_tx3g4c28phy_start()
116 hdmi->event_received = false; in sti_hdmi_tx3g4c28phy_start()
121 wait_event_interruptible_timeout(hdmi->wait_event, in sti_hdmi_tx3g4c28phy_start()
122 hdmi->event_received == true, in sti_hdmi_tx3g4c28phy_start()
142 * To configure the source termination and pre-emphasis appropriately in sti_hdmi_tx3g4c28phy_start()
168 * Default, power up the serializer with no pre-emphasis or in sti_hdmi_tx3g4c28phy_start()
182 * sti_hdmi_tx3g4c28phy_stop - Stop hdmi phy macro cell tx3g4c28
192 hdmi->event_received = false; in sti_hdmi_tx3g4c28phy_stop()
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/Linux-v5.15/include/sound/
Dak4117.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
27 #define AK4117_REG_QSUB_ADDR 0x11 /* Q-subcode address + control */
28 #define AK4117_REG_QSUB_TRACK 0x12 /* Q-subcode track */
29 #define AK4117_REG_QSUB_INDEX 0x13 /* Q-subcode index */
30 #define AK4117_REG_QSUB_MINUTE 0x14 /* Q-subcode minute */
31 #define AK4117_REG_QSUB_SECOND 0x15 /* Q-subcode second */
32 #define AK4117_REG_QSUB_FRAME 0x16 /* Q-subcode frame */
33 #define AK4117_REG_QSUB_ZERO 0x17 /* Q-subcode zero */
34 #define AK4117_REG_QSUB_ABSMIN 0x18 /* Q-subcode absolute minute */
35 #define AK4117_REG_QSUB_ABSSEC 0x19 /* Q-subcode absolute second */
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Dak4113.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
50 /* Q-subcode address + control */
52 /* Q-subcode track */
54 /* Q-subcode index */
56 /* Q-subcode minute */
58 /* Q-subcode second */
60 /* Q-subcode frame */
62 /* Q-subcode zero */
64 /* Q-subcode absolute minute */
66 /* Q-subcode absolute second */
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Dak4114.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
33 #define AK4114_REG_QSUB_ADDR 0x16 /* Q-subcode address + control */
34 #define AK4114_REG_QSUB_TRACK 0x17 /* Q-subcode track */
35 #define AK4114_REG_QSUB_INDEX 0x18 /* Q-subcode index */
36 #define AK4114_REG_QSUB_MINUTE 0x19 /* Q-subcode minute */
37 #define AK4114_REG_QSUB_SECOND 0x1a /* Q-subcode second */
38 #define AK4114_REG_QSUB_FRAME 0x1b /* Q-subcode frame */
39 #define AK4114_REG_QSUB_ZERO 0x1c /* Q-subcode zero */
40 #define AK4114_REG_QSUB_ABSMIN 0x1d /* Q-subcode absolute minute */
41 #define AK4114_REG_QSUB_ABSSEC 0x1e /* Q-subcode absolute second */
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/Linux-v5.15/drivers/gpu/drm/msm/edp/
Dedp_phy.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
20 while (--cnt) { in msm_edp_phy_ready()
21 status = edp_read(phy->base + in msm_edp_phy_ready()
41 edp_write(phy->base + REG_EDP_PHY_CTRL, in msm_edp_phy_ctrl()
46 edp_write(phy->base + REG_EDP_PHY_CTRL, 0x000); in msm_edp_phy_ctrl()
47 edp_write(phy->base + REG_EDP_PHY_GLB_PD_CTL, 0x3f); in msm_edp_phy_ctrl()
48 edp_write(phy->base + REG_EDP_PHY_GLB_CFG, 0x1); in msm_edp_phy_ctrl()
50 edp_write(phy->base + REG_EDP_PHY_GLB_PD_CTL, 0xc0); in msm_edp_phy_ctrl()
54 /* voltage mode and pre emphasis cfg */
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/Linux-v5.15/drivers/gpu/drm/tegra/
Ddp.h1 /* SPDX-License-Identifier: MIT */
3 * Copyright (C) 2013-2019 NVIDIA Corporation.
18 * struct drm_dp_link_caps - DP link capabilities
61 * struct drm_dp_link_ops - DP link operations
80 * struct drm_dp_link_train_set - link training settings
81 * @voltage_swing: per-lane voltage swing
82 * @pre_emphasis: per-lane pre-emphasis
83 * @post_cursor: per-lane post-cursor
92 * struct drm_dp_link_train - link training state information
110 * struct drm_dp_link - DP link capabilities and configuration
/Linux-v5.15/drivers/media/radio/wl128x/
Dfmdrv_common.h1 /* SPDX-License-Identifier: GPL-2.0-only */
129 #define fm_cb(skb) ((struct fm_skb_cb *)(skb->cb))
131 /* FM Channel-8 command message format */
133 __u8 hdr; /* Logical Channel-8 */
142 /* FM Channel-8 event messgage format */
144 __u8 header; /* Logical Channel-8 */
223 #define FM_RX_RSSI_THRESHOLD_MIN -128
231 /* FM RX De-emphasis filter modes */
347 /* FM TX Pre-emphasis filter values */
357 /* Functions exported by FM common sub-module */
Dfmdrv_tx.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * This sub-module of FM driver implements FM TX functionality.
19 if (fmdev->tx_data.aud_mode == mode) in fm_tx_set_stereo_mono()
25 payload = (1 - mode); in fm_tx_set_stereo_mono()
31 fmdev->tx_data.aud_mode = mode; in fm_tx_set_stereo_mono()
133 fmdev->tx_data.rds.flag = rds_en_dis; in fm_tx_set_rds_mode()
143 if (fmdev->curr_fmmode != FM_MODE_TX) in fm_tx_set_radio_text()
144 return -EPERM; in fm_tx_set_radio_text()
171 if (fmdev->curr_fmmode != FM_MODE_TX) in fm_tx_set_af()
172 return -EPERM; in fm_tx_set_af()
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/Linux-v5.15/Documentation/devicetree/bindings/usb/
Dci-hdrc-usb2.txt4 - compatible: should be one of:
5 "fsl,imx23-usb"
6 "fsl,imx27-usb"
7 "fsl,imx28-usb"
8 "fsl,imx6q-usb"
9 "fsl,imx6sl-usb"
10 "fsl,imx6sx-usb"
11 "fsl,imx6ul-usb"
12 "fsl,imx7d-usb"
13 "fsl,imx7ulp-usb"
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/Linux-v5.15/drivers/phy/lantiq/
Dphy-lantiq-rcu-usb2.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * Copyright (C) 2017 Hauke Mehrtens <hauke@hauke-m.de>
22 /* Transmitter HS Pre-Emphasis Enable */
70 .compatible = "lantiq,ase-usb2-phy",
74 .compatible = "lantiq,danube-usb2-phy",
78 .compatible = "lantiq,xrx100-usb2-phy",
82 .compatible = "lantiq,xrx200-usb2-phy",
86 .compatible = "lantiq,xrx300-usb2-phy",
97 if (priv->reg_bits->have_ana_cfg) { in ltq_rcu_usb2_phy_init()
98 regmap_update_bits(priv->regmap, priv->ana_cfg1_reg_offset, in ltq_rcu_usb2_phy_init()
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/Linux-v5.15/drivers/gpu/drm/amd/amdgpu/
Datombios_dp.c2 * Copyright 2007-8 Advanced Micro Devices, Inc.
32 #include "atom-bits.h"
62 struct drm_device *dev = chan->dev; in amdgpu_atombios_dp_process_aux_ch()
72 mutex_lock(&chan->mutex); in amdgpu_atombios_dp_process_aux_ch()
74 base = (unsigned char *)(adev->mode_info.atom_context->scratch + 1); in amdgpu_atombios_dp_process_aux_ch()
81 args.v2.ucChannelID = chan->rec.i2c_id; in amdgpu_atombios_dp_process_aux_ch()
83 args.v2.ucHPD_ID = chan->rec.hpd; in amdgpu_atombios_dp_process_aux_ch()
85 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); in amdgpu_atombios_dp_process_aux_ch()
91 r = -ETIMEDOUT; in amdgpu_atombios_dp_process_aux_ch()
98 r = -EIO; in amdgpu_atombios_dp_process_aux_ch()
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/Linux-v5.15/drivers/phy/xilinx/
Dphy-zynqmp.c1 // SPDX-License-Identifier: GPL-2.0
3 * phy-zynqmp.c - PHY driver for Xilinx ZynqMP GT.
5 * Copyright (C) 2018-2020 Xilinx Inc.
26 #include <dt-bindings/phy/phy.h>
32 /* TX De-emphasis parameters */
170 * struct xpsgtr_ssc - structure to hold SSC settings for a lane
184 * struct xpsgtr_phy - representation of a lane
204 * struct xpsgtr_dev - representation of a ZynMP GT device
256 return readl(gtr_dev->serdes + reg); in xpsgtr_read()
261 writel(value, gtr_dev->serdes + reg); in xpsgtr_write()
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/Linux-v5.15/drivers/gpu/drm/bridge/cadence/
Dcdns-mhdp8546-core.c1 // SPDX-License-Identifier: GPL-2.0
7 * Authors: Quentin Schulz <quentin.schulz@free-electrons.com>
14 * - Implement optimized mailbox communication using mailbox interrupts
15 * - Add support for power management
16 * - Add support for features like audio, MST and fast link training
17 * - Implement request_fw_cancel to handle HW_STATE
18 * - Fix asynchronous loading of firmware implementation
19 * - Add DRM helper function for cdns_mhdp_lower_link_rate
33 #include <linux/phy/phy-dp.h>
52 #include "cdns-mhdp8546-core.h"
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/Linux-v5.15/drivers/phy/cadence/
Dphy-cadence-torrent.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <dt-bindings/phy/phy.h>
10 #include <dt-bindings/phy/phy-cadence.h>
12 #include <linux/clk-provider.h>
239 [CDNS_TORRENT_REFCLK_DRIVER] = "refclk-driver",
393 u32 offset = reg << ctx->reg_offset_shift; in cdns_regmap_write()
395 writew(val, ctx->base + offset); in cdns_regmap_write()
403 u32 offset = reg << ctx->reg_offset_shift; in cdns_regmap_read()
405 *val = readw(ctx->base + offset); in cdns_regmap_read()
415 writel(val, ctx->base + offset); in cdns_regmap_dptx_write()
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/Linux-v5.15/drivers/phy/
Dphy-xgene.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * AppliedMicro X-Gene Multi-purpose PHY driver
10 * The APM X-Gene PHY consists of two PLL clock macro's (CMU) and lanes.
19 * -----------------
20 * | Internal | |------|
21 * | Ref PLL CMU |----| | ------------- ---------
22 * ------------ ---- | MUX |-----|PHY PLL CMU|----| Serdes|
23 * | | | | ---------
24 * External Clock ------| | -------------
25 * |------|
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/Linux-v5.15/drivers/gpu/drm/radeon/
Datombios_dp.c2 * Copyright 2007-8 Advanced Micro Devices, Inc.
32 #include "atom-bits.h"
90 struct drm_device *dev = chan->dev; in radeon_process_aux_ch()
91 struct radeon_device *rdev = dev->dev_private; in radeon_process_aux_ch()
100 mutex_lock(&chan->mutex); in radeon_process_aux_ch()
101 mutex_lock(&rdev->mode_info.atom_context->scratch_mutex); in radeon_process_aux_ch()
103 base = (unsigned char *)(rdev->mode_info.atom_context->scratch + 1); in radeon_process_aux_ch()
110 args.v1.ucChannelID = chan->rec.i2c_id; in radeon_process_aux_ch()
113 args.v2.ucHPD_ID = chan->rec.hpd; in radeon_process_aux_ch()
115 atom_execute_table_scratch_unlocked(rdev->mode_info.atom_context, index, (uint32_t *)&args); in radeon_process_aux_ch()
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/Linux-v5.15/drivers/gpu/drm/i915/display/
Dintel_ddi_buf_trans.c1 // SPDX-License-Identifier: MIT
397 /* BSpec has 2 recommended values - entries 0 and 8.
417 .hdmi_default_entry = ARRAY_SIZE(_bxt_ddi_translations_hdmi) - 1,
473 .hdmi_default_entry = ARRAY_SIZE(_icl_combo_phy_ddi_translations_hdmi) - 1,
591 /* Voltage swing pre-emphasis */
610 /* Voltage swing pre-emphasis */
629 /* HDMI Preset VS Pre-emph */
635 { .mg = { 0x3A, 0x0, 0x5 } }, /* 6 Full -1.5 dB */
636 { .mg = { 0x39, 0x0, 0x6 } }, /* 7 Full -1.8 dB */
637 { .mg = { 0x38, 0x0, 0x7 } }, /* 8 Full -2 dB */
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/Linux-v5.15/drivers/media/v4l2-core/
Dv4l2-ctrls-defs.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (C) 2010-2021 Hans Verkuil <hverkuil-cisco@xs4all.nl>
9 #include <media/v4l2-ctrls.h>
26 "MPEG-1/2 Layer I", in v4l2_ctrl_get_menu()
27 "MPEG-1/2 Layer II", in v4l2_ctrl_get_menu()
28 "MPEG-1/2 Layer III", in v4l2_ctrl_get_menu()
29 "MPEG-2/4 AAC", in v4l2_ctrl_get_menu()
30 "AC-3", in v4l2_ctrl_get_menu()
121 "No Emphasis", in v4l2_ctrl_get_menu()
128 "16-bit CRC", in v4l2_ctrl_get_menu()
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/Linux-v5.15/drivers/phy/qualcomm/
Dphy-qcom-qusb2.c1 // SPDX-License-Identifier: GPL-2.0
13 #include <linux/nvmem-consumer.h>
23 #include <dt-bindings/phy/phy-qcom-qusb2.h>
106 * if yes, then offset gives index in the reg-layout
124 /* set of registers with offsets different per-PHY */
295 /* true if PHY default clk scheme is single-ended */
374 "vdda-pll", "vdda-phy-dpdm",
379 /* struct override_param - structure holding qusb2 v2 phy overriding param
388 /*struct override_params - structure holding qusb2 v2 phy overriding params
391 * @preemphasis: Amplitude Pre-Emphasis to be updated in TUNE1 register
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/Linux-v5.15/drivers/gpu/drm/msm/dp/
Ddp_link.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2012-2020, The Linux Foundation. All rights reserved.
6 #define pr_fmt(fmt) "[drm-dp] %s: " fmt, __func__
53 if (link->revision < 0x11) in dp_aux_link_power_up()
78 if (link->revision < 0x11) in dp_aux_link_power_down()
102 if (drm_dp_dpcd_readb(link->aux, addr, &data) < 0) { in dp_link_get_period()
104 ret = -EINVAL; in dp_link_get_period()
108 /* Period - Bits 3:0 */ in dp_link_get_period()
112 ret = -EINVAL; in dp_link_get_period()
124 struct dp_link_test_audio *req = &link->dp_link.test_audio; in dp_link_parse_audio_channel_period()
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