Searched +full:power +full:- +full:sample +full:- +full:average (Results 1 – 25 of 82) sorted by relevance
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| /Linux-v6.1/Documentation/devicetree/bindings/hwmon/ |
| D | adi,adm1275.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Analog Devices ADM1075/ADM127x/ADM129x digital power monitors
11 - Krzysztof Kozlowski <krzk@kernel.org>
14 The ADM1293 and ADM1294 are high accuracy integrated digital power monitors
15 that offer digital current, voltage, and power monitoring using an on-chip,
16 12-bit analog-to-digital converter (ADC), communicated through a PMBus
25 - adi,adm1075
26 - adi,adm1272
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|
| /Linux-v6.1/Documentation/hwmon/ |
| D | fam15h_power.rst | 16 - BIOS and Kernel Developer's Guide (BKDG) For AMD Family 15h Processors
17 - BIOS and Kernel Developer's Guide (BKDG) For AMD Family 16h Processors
18 - AMD64 Architecture Programmer's Manual Volume 2: System Programming
23 -----------
25 1) Processor TDP (Thermal design power)
27 Given a fixed frequency and voltage, the power consumption of a
28 processor varies based on the workload being executed. Derated power
29 is the power consumed when running a specific application. Thermal
30 design power (TDP) is an example of derated power.
32 This driver permits reading of registers providing power information
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|
| D | sysfs-interface.rst | 5 through the sysfs interface. Since lm-sensors 3.0.0, libsensors is
6 completely chip-independent. It assumes that all the kernel drivers
10 This is a major improvement compared to lm-sensors 2.
22 For this reason, even if we aim at a chip-independent libsensors, it will
37 Up to lm-sensors 3.0.0, libsensors looks for hardware monitoring attributes
38 in the "physical" device directory. Since lm-sensors 3.0.1, attributes found
61 to cause an alarm) is chip-dependent.
69 ----------------
76 -------------------------------------------------------------------------
79 `[0-*]` denotes any positive number starting from 0
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| /Linux-v6.1/tools/perf/pmu-events/arch/x86/cascadelakex/ |
| D | clx-metrics.json | 7 …-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into mi…
15 …-cache misses; iTLB misses or fetch stalls after a branch misprediction are categorized under Fron…
23 … fraction of cycles the CPU was stalled due to instruction cache misses. Sample with: FRONTEND_RET…
31 …tion of cycles the CPU was stalled due to Instruction TLB (ITLB) misses. Sample with: FRONTEND_RET…
39 …-predicted branches. For example; branchy code with lots of miss-predictions might get categorized…
47 …Branch Resteers as a result of Branch Misprediction at execution stage. Sample with: INT_MISC.CLE…
52 …"MetricExpr": "(1 - (BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS…
55 …e CPU was stalled due to Branch Resteers as a result of Machine Clears. Sample with: INT_MISC.CLE…
63 …nit was unable to recognize (First fetch or hitting BPU capacity limit). Sample with: BACLEARS.ANY…
71 …-cache) is a Uop Cache where the front-end directly delivers Uops (micro operations) avoiding heav…
[all …]
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| /Linux-v6.1/tools/perf/pmu-events/arch/x86/haswell/ |
| D | hsw-metrics.json | 7 …-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into mi…
15 …-cache misses; iTLB misses or fetch stalls after a branch misprediction are categorized under Fron…
30 …tion of cycles the CPU was stalled due to Instruction TLB (ITLB) misses. Sample with: ITLB_MISSES.…
38 …-predicted branches. For example; branchy code with lots of miss-predictions might get categorized…
46 …o switches from DSB to MITE pipelines. The DSB (decoded i-cache) is a Uop Cache where the front-en…
62 …-cache) or MITE (legacy instruction decode) pipelines. Certain operations cannot be handled native…
67 "MetricExpr": "tma_frontend_bound - tma_fetch_latency",
75 "MetricExpr": "(IDQ.ALL_MITE_CYCLES_ANY_UOPS - IDQ.ALL_MITE_CYCLES_4_UOPS) / CORE_CLKS / 2",
78 …the legacy decode pipeline). This pipeline is used for code that was not pre-cached in the DSB or …
83 "MetricExpr": "(IDQ.ALL_DSB_CYCLES_ANY_UOPS - IDQ.ALL_DSB_CYCLES_4_UOPS) / CORE_CLKS / 2",
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| /Linux-v6.1/tools/perf/pmu-events/arch/x86/icelakex/ |
| D | icx-metrics.json | 4 …"MetricExpr": "topdown\\-fe\\-bound / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-ret…
7 …-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into mi…
12 …"MetricExpr": "(5 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE - INT_MISC.UOP_DROPPING) / SLO…
15 …-cache misses; iTLB misses or fetch stalls after a branch misprediction are categorized under Fron…
23 … fraction of cycles the CPU was stalled due to instruction cache misses. Sample with: FRONTEND_RET…
31 …tion of cycles the CPU was stalled due to Instruction TLB (ITLB) misses. Sample with: FRONTEND_RET…
39 …-predicted branches. For example; branchy code with lots of miss-predictions might get categorized…
47 …Branch Resteers as a result of Branch Misprediction at execution stage. Sample with: INT_MISC.CLE…
52 …"MetricExpr": "(1 - (BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS…
55 …e CPU was stalled due to Branch Resteers as a result of Machine Clears. Sample with: INT_MISC.CLE…
[all …]
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| /Linux-v6.1/tools/perf/pmu-events/arch/x86/ivybridge/ |
| D | ivb-metrics.json | 7 …-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into mi…
15 …-cache misses; iTLB misses or fetch stalls after a branch misprediction are categorized under Fron…
20 "MetricExpr": "ICACHE.IFETCH_STALL / CLKS - tma_itlb_misses",
30 …tion of cycles the CPU was stalled due to Instruction TLB (ITLB) misses. Sample with: ITLB_MISSES.…
38 …-predicted branches. For example; branchy code with lots of miss-predictions might get categorized…
46 …o switches from DSB to MITE pipelines. The DSB (decoded i-cache) is a Uop Cache where the front-en…
62 …-cache) or MITE (legacy instruction decode) pipelines. Certain operations cannot be handled native…
67 "MetricExpr": "tma_frontend_bound - tma_fetch_latency",
75 "MetricExpr": "(IDQ.ALL_MITE_CYCLES_ANY_UOPS - IDQ.ALL_MITE_CYCLES_4_UOPS) / CORE_CLKS / 2",
78 …the legacy decode pipeline). This pipeline is used for code that was not pre-cached in the DSB or …
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| /Linux-v6.1/tools/perf/pmu-events/arch/x86/skylakex/ |
| D | skx-metrics.json | 7 …-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into mi…
15 …-cache misses; iTLB misses or fetch stalls after a branch misprediction are categorized under Fron…
23 … fraction of cycles the CPU was stalled due to instruction cache misses. Sample with: FRONTEND_RET…
31 …tion of cycles the CPU was stalled due to Instruction TLB (ITLB) misses. Sample with: FRONTEND_RET…
39 …-predicted branches. For example; branchy code with lots of miss-predictions might get categorized…
47 …Branch Resteers as a result of Branch Misprediction at execution stage. Sample with: INT_MISC.CLE…
52 …"MetricExpr": "(1 - (BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS…
55 …e CPU was stalled due to Branch Resteers as a result of Machine Clears. Sample with: INT_MISC.CLE…
63 …nit was unable to recognize (First fetch or hitting BPU capacity limit). Sample with: BACLEARS.ANY…
71 …-cache) is a Uop Cache where the front-end directly delivers Uops (micro operations) avoiding heav…
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| /Linux-v6.1/tools/perf/pmu-events/arch/x86/sandybridge/ |
| D | snb-metrics.json | 7 …-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into mi…
15 …-cache misses; iTLB misses or fetch stalls after a branch misprediction are categorized under Fron…
23 …tion of cycles the CPU was stalled due to Instruction TLB (ITLB) misses. Sample with: ITLB_MISSES.…
31 …-predicted branches. For example; branchy code with lots of miss-predictions might get categorized…
39 …o switches from DSB to MITE pipelines. The DSB (decoded i-cache) is a Uop Cache where the front-en…
55 …-cache) or MITE (legacy instruction decode) pipelines. Certain operations cannot be handled native…
60 "MetricExpr": "tma_frontend_bound - tma_fetch_latency",
68 …"MetricExpr": "(UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * ((INT_MISC.RECOVERY_CYCLES_ANY /…
71 …s for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For…
79 …ram path; or stalls when the out-of-order part of the machine needs to recover its state from a sp…
[all …]
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| /Linux-v6.1/tools/perf/pmu-events/arch/x86/tigerlake/ |
| D | tgl-metrics.json | 4 …"MetricExpr": "topdown\\-fe\\-bound / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-ret…
7 …-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into mi…
12 …"MetricExpr": "(5 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE - INT_MISC.UOP_DROPPING) / SLO…
15 …-cache misses; iTLB misses or fetch stalls after a branch misprediction are categorized under Fron…
23 … fraction of cycles the CPU was stalled due to instruction cache misses. Sample with: FRONTEND_RET…
31 …tion of cycles the CPU was stalled due to Instruction TLB (ITLB) misses. Sample with: FRONTEND_RET…
39 …-predicted branches. For example; branchy code with lots of miss-predictions might get categorized…
47 …Branch Resteers as a result of Branch Misprediction at execution stage. Sample with: INT_MISC.CLE…
52 …"MetricExpr": "(1 - (BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS…
55 …e CPU was stalled due to Branch Resteers as a result of Machine Clears. Sample with: INT_MISC.CLE…
[all …]
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| /Linux-v6.1/tools/perf/pmu-events/arch/x86/icelake/ |
| D | icl-metrics.json | 4 …"MetricExpr": "topdown\\-fe\\-bound / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-ret…
7 …-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into mi…
12 …"MetricExpr": "(5 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE - INT_MISC.UOP_DROPPING) / SLO…
15 …-cache misses; iTLB misses or fetch stalls after a branch misprediction are categorized under Fron…
23 … fraction of cycles the CPU was stalled due to instruction cache misses. Sample with: FRONTEND_RET…
31 …tion of cycles the CPU was stalled due to Instruction TLB (ITLB) misses. Sample with: FRONTEND_RET…
39 …-predicted branches. For example; branchy code with lots of miss-predictions might get categorized…
47 …Branch Resteers as a result of Branch Misprediction at execution stage. Sample with: INT_MISC.CLE…
52 …"MetricExpr": "(1 - (BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS…
55 …e CPU was stalled due to Branch Resteers as a result of Machine Clears. Sample with: INT_MISC.CLE…
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| /Linux-v6.1/tools/perf/pmu-events/arch/x86/broadwellde/ |
| D | bdwde-metrics.json | 7 …-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into mi…
15 …-cache misses; iTLB misses or fetch stalls after a branch misprediction are categorized under Fron…
23 … fraction of cycles the CPU was stalled due to instruction cache misses. Sample with: FRONTEND_RET…
31 …tion of cycles the CPU was stalled due to Instruction TLB (ITLB) misses. Sample with: FRONTEND_RET…
39 …-predicted branches. For example; branchy code with lots of miss-predictions might get categorized…
47 …Branch Resteers as a result of Branch Misprediction at execution stage. Sample with: INT_MISC.CLE…
55 …e CPU was stalled due to Branch Resteers as a result of Machine Clears. Sample with: INT_MISC.CLE…
60 "MetricExpr": "tma_branch_resteers - tma_mispredicts_resteers - tma_clears_resteers",
63 …nit was unable to recognize (First fetch or hitting BPU capacity limit). Sample with: FRONTEND_RET…
71 …-cache) is a Uop Cache where the front-end directly delivers Uops (micro operations) avoiding heav…
[all …]
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| /Linux-v6.1/tools/perf/pmu-events/arch/x86/ivytown/ |
| D | ivt-metrics.json | 7 …-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into mi…
15 …-cache misses; iTLB misses or fetch stalls after a branch misprediction are categorized under Fron…
20 "MetricExpr": "ICACHE.IFETCH_STALL / CLKS - tma_itlb_misses",
30 …tion of cycles the CPU was stalled due to Instruction TLB (ITLB) misses. Sample with: ITLB_MISSES.…
38 …-predicted branches. For example; branchy code with lots of miss-predictions might get categorized…
46 …o switches from DSB to MITE pipelines. The DSB (decoded i-cache) is a Uop Cache where the front-en…
62 …-cache) or MITE (legacy instruction decode) pipelines. Certain operations cannot be handled native…
67 "MetricExpr": "tma_frontend_bound - tma_fetch_latency",
75 "MetricExpr": "(IDQ.ALL_MITE_CYCLES_ANY_UOPS - IDQ.ALL_MITE_CYCLES_4_UOPS) / CORE_CLKS / 2",
78 …the legacy decode pipeline). This pipeline is used for code that was not pre-cached in the DSB or …
[all …]
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| /Linux-v6.1/tools/perf/pmu-events/arch/x86/haswellx/ |
| D | hsx-metrics.json | 7 …-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into mi…
15 …-cache misses; iTLB misses or fetch stalls after a branch misprediction are categorized under Fron…
30 …tion of cycles the CPU was stalled due to Instruction TLB (ITLB) misses. Sample with: ITLB_MISSES.…
38 …-predicted branches. For example; branchy code with lots of miss-predictions might get categorized…
46 …o switches from DSB to MITE pipelines. The DSB (decoded i-cache) is a Uop Cache where the front-en…
62 …-cache) or MITE (legacy instruction decode) pipelines. Certain operations cannot be handled native…
67 "MetricExpr": "tma_frontend_bound - tma_fetch_latency",
75 "MetricExpr": "(IDQ.ALL_MITE_CYCLES_ANY_UOPS - IDQ.ALL_MITE_CYCLES_4_UOPS) / CORE_CLKS / 2",
78 …the legacy decode pipeline). This pipeline is used for code that was not pre-cached in the DSB or …
83 "MetricExpr": "(IDQ.ALL_DSB_CYCLES_ANY_UOPS - IDQ.ALL_DSB_CYCLES_4_UOPS) / CORE_CLKS / 2",
[all …]
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| /Linux-v6.1/tools/perf/pmu-events/arch/x86/broadwell/ |
| D | bdw-metrics.json | 7 …-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into mi…
15 …-cache misses; iTLB misses or fetch stalls after a branch misprediction are categorized under Fron…
30 …tion of cycles the CPU was stalled due to Instruction TLB (ITLB) misses. Sample with: ITLB_MISSES.…
38 …-predicted branches. For example; branchy code with lots of miss-predictions might get categorized…
57 "MetricExpr": "tma_branch_resteers - tma_mispredicts_resteers - tma_clears_resteers",
60 …nit was unable to recognize (First fetch or hitting BPU capacity limit). Sample with: BACLEARS.ANY…
68 …o switches from DSB to MITE pipelines. The DSB (decoded i-cache) is a Uop Cache where the front-en…
84 …-cache) or MITE (legacy instruction decode) pipelines. Certain operations cannot be handled native…
89 "MetricExpr": "tma_frontend_bound - tma_fetch_latency",
97 "MetricExpr": "(IDQ.ALL_MITE_CYCLES_ANY_UOPS - IDQ.ALL_MITE_CYCLES_4_UOPS) / CORE_CLKS / 2",
[all …]
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| /Linux-v6.1/tools/perf/pmu-events/arch/x86/skylake/ |
| D | skl-metrics.json | 7 …-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into mi…
15 …-cache misses; iTLB misses or fetch stalls after a branch misprediction are categorized under Fron…
23 … fraction of cycles the CPU was stalled due to instruction cache misses. Sample with: FRONTEND_RET…
31 …tion of cycles the CPU was stalled due to Instruction TLB (ITLB) misses. Sample with: FRONTEND_RET…
39 …-predicted branches. For example; branchy code with lots of miss-predictions might get categorized…
47 …Branch Resteers as a result of Branch Misprediction at execution stage. Sample with: INT_MISC.CLE…
52 …"MetricExpr": "(1 - (BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS…
55 …e CPU was stalled due to Branch Resteers as a result of Machine Clears. Sample with: INT_MISC.CLE…
63 …nit was unable to recognize (First fetch or hitting BPU capacity limit). Sample with: BACLEARS.ANY…
71 …-cache) is a Uop Cache where the front-end directly delivers Uops (micro operations) avoiding heav…
[all …]
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| /Linux-v6.1/kernel/sched/ |
| D | loadavg.c | 1 // SPDX-License-Identifier: GPL-2.0
11 * Global load-average calculations
13 * We take a distributed and async approach to calculating the global load-avg
16 * The global load average is an exponentially decaying average of nr_running +
23 * nr_active += cpu_of(cpu)->nr_running + cpu_of(cpu)->nr_uninterruptible;
25 * avenrun[n] = avenrun[0] * exp_n + nr_active * (1 - exp_n)
29 * - for_each_possible_cpu() is prohibitively expensive on machines with
33 * \Sum_i x_i(t) = \Sum_i x_i(t) - x_i(t_0) | x_i(t_0) := 0
34 * = \Sum_i { \Sum_j=1 x_i(t_j) - x_i(t_j-1) }
36 * So assuming nr_active := 0 when we start out -- true per definition, we
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| /Linux-v6.1/tools/perf/pmu-events/arch/x86/jaketown/ |
| D | jkt-metrics.json | 7 …-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into mi…
15 …-cache misses; iTLB misses or fetch stalls after a branch misprediction are categorized under Fron…
23 …tion of cycles the CPU was stalled due to Instruction TLB (ITLB) misses. Sample with: ITLB_MISSES.…
31 …-predicted branches. For example; branchy code with lots of miss-predictions might get categorized…
39 …o switches from DSB to MITE pipelines. The DSB (decoded i-cache) is a Uop Cache where the front-en…
55 …-cache) or MITE (legacy instruction decode) pipelines. Certain operations cannot be handled native…
60 "MetricExpr": "tma_frontend_bound - tma_fetch_latency",
68 …"MetricExpr": "(UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * ((INT_MISC.RECOVERY_CYCLES_ANY /…
71 …s for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For…
79 …ram path; or stalls when the out-of-order part of the machine needs to recover its state from a sp…
[all …]
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| /Linux-v6.1/tools/perf/pmu-events/arch/x86/broadwellx/ |
| D | bdx-metrics.json | 7 …-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into mi…
15 …-cache misses; iTLB misses or fetch stalls after a branch misprediction are categorized under Fron…
30 …tion of cycles the CPU was stalled due to Instruction TLB (ITLB) misses. Sample with: ITLB_MISSES.…
38 …-predicted branches. For example; branchy code with lots of miss-predictions might get categorized…
57 "MetricExpr": "tma_branch_resteers - tma_mispredicts_resteers - tma_clears_resteers",
60 …nit was unable to recognize (First fetch or hitting BPU capacity limit). Sample with: BACLEARS.ANY…
68 …o switches from DSB to MITE pipelines. The DSB (decoded i-cache) is a Uop Cache where the front-en…
84 …-cache) or MITE (legacy instruction decode) pipelines. Certain operations cannot be handled native…
89 "MetricExpr": "tma_frontend_bound - tma_fetch_latency",
97 "MetricExpr": "(IDQ.ALL_MITE_CYCLES_ANY_UOPS - IDQ.ALL_MITE_CYCLES_4_UOPS) / CORE_CLKS / 2",
[all …]
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| /Linux-v6.1/tools/perf/pmu-events/arch/x86/alderlake/ |
| D | adl-metrics.json | 4 …"MetricExpr": "topdown\\-fe\\-bound / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-ret…
7 …-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into mi…
13 …etricExpr": "(topdown\\-fetch\\-lat / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-ret…
16 …-cache misses; iTLB misses or fetch stalls after a branch misprediction are categorized under Fron…
25 … fraction of cycles the CPU was stalled due to instruction cache misses. Sample with: FRONTEND_RET…
34 …tion of cycles the CPU was stalled due to Instruction TLB (ITLB) misses. Sample with: FRONTEND_RET…
43 …-predicted branches. For example; branchy code with lots of miss-predictions might get categorized…
52 …Branch Resteers as a result of Branch Misprediction at execution stage. Sample with: INT_MISC.CLE…
58 …"MetricExpr": "(1 - (tma_branch_mispredicts / tma_bad_speculation)) * INT_MISC.CLEAR_RESTEER_CYCLE…
61 …e CPU was stalled due to Branch Resteers as a result of Machine Clears. Sample with: INT_MISC.CLE…
[all …]
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| /Linux-v6.1/tools/power/cpupower/bench/ |
| D | README-BENCH | 1 This is cpufreq-bench, a microbenchmark for the cpufreq framework.
7 - Identify worst case performance loss when doing dynamic frequency
9 - Identify average reaction time of a governor to CPU load changes
10 - (Stress) Testing whether a cpufreq low level driver or governor works
12 - Identify cpufreq related performance regressions between kernels
13 - Possibly Real time priority testing? -> what happens if there are
15 - ...
18 - Power saving related regressions (In fact as better the performance
19 throughput is, the worse the power savings will be, but the first should
21 - Real world (workloads)
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| /Linux-v6.1/tools/perf/pmu-events/arch/x86/sapphirerapids/ |
| D | spr-metrics.json | 4 …"MetricExpr": "topdown\\-fe\\-bound / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-ret…
7 …-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into mi…
12 …etricExpr": "(topdown\\-fetch\\-lat / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-ret…
15 …-cache misses; iTLB misses or fetch stalls after a branch misprediction are categorized under Fron…
23 … fraction of cycles the CPU was stalled due to instruction cache misses. Sample with: FRONTEND_RET…
31 …tion of cycles the CPU was stalled due to Instruction TLB (ITLB) misses. Sample with: FRONTEND_RET…
39 …-predicted branches. For example; branchy code with lots of miss-predictions might get categorized…
47 …Branch Resteers as a result of Branch Misprediction at execution stage. Sample with: INT_MISC.CLE…
52 …"MetricExpr": "(1 - (tma_branch_mispredicts / tma_bad_speculation)) * INT_MISC.CLEAR_RESTEER_CYCLE…
55 …e CPU was stalled due to Branch Resteers as a result of Machine Clears. Sample with: INT_MISC.CLE…
[all …]
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| /Linux-v6.1/tools/perf/Documentation/ |
| D | perf-kvm.txt | 1 perf-kvm(1)
5 ----
6 perf-kvm - Tool to trace/measure kvm guest os
9 --------
11 'perf kvm' [--host] [--guest] [--guestmount=<path>
12 [--guestkallsyms=<path> --guestmodules=<path> | --guestvmlinux=<path>]]
13 {top|record|report|diff|buildid-list} [<options>]
14 'perf kvm' [--host] [--guest] [--guestkallsyms=<path> --guestmodules=<path>
15 | --guestvmlinux=<path>] {top|record|report|diff|buildid-list|stat} [<options>]
19 -----------
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| /Linux-v6.1/tools/power/x86/turbostat/ |
| D | turbostat.8 | 3 turbostat \- Report processor frequency and idle statistics
12 .RB [ "\--interval seconds" ]
15 idle power-state statistics, temperature and power on X86 processors.
19 in one-shot upon its completion.
22 The 5-second interval can be changed using the --interval option.
26 Options can be specified with a single or double '-', and only as much of the option
27 name as necessary to disambiguate it from others is necessary. Note that options are case-sensitiv…
29 \fB--add attributes\fP add column with counter having specified 'attributes'. The 'location' attri…
37 sample and print the counter for every cpu, core, or package.
41 MSRs are read as 64-bits, u32 truncates the displayed value to 32-bits.
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| /Linux-v6.1/drivers/iio/adc/ |
| D | vf610_adc.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
30 #define DRIVER_NAME "vf610-adc"
181 struct vf610_adc_feature *adc_feature = &info->adc_feature; in vf610_adc_calculate_rates()
182 unsigned long adck_rate, ipg_rate = clk_get_rate(info->clk); in vf610_adc_calculate_rates()
186 adck_rate = info->max_adck_rate[adc_feature->conv_mode]; in vf610_adc_calculate_rates()
191 adc_feature->clk_div = 1 << fls(divisor + 1); in vf610_adc_calculate_rates()
193 /* fall-back value using a safe divisor */ in vf610_adc_calculate_rates()
194 adc_feature->clk_div = 8; in vf610_adc_calculate_rates()
197 adck_rate = ipg_rate / adc_feature->clk_div; in vf610_adc_calculate_rates()
200 * Determine the long sample time adder value to be used based in vf610_adc_calculate_rates()
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