Searched +full:post +full:- +full:delay (Results 1 – 25 of 525) sorted by relevance
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| /Linux-v5.15/Documentation/devicetree/bindings/leds/backlight/ |
| D | pwm-backlight.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/leds/backlight/pwm-backlight.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: pwm-backlight bindings
10 - Lee Jones <lee.jones@linaro.org>
11 - Daniel Thompson <daniel.thompson@linaro.org>
12 - Jingoo Han <jingoohan1@gmail.com>
16 const: pwm-backlight
21 pwm-names: true
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| /Linux-v5.15/Documentation/devicetree/bindings/net/ |
| D | fsl,fec.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Joakim Zhang <qiangqing.zhang@nxp.com>
13 - $ref: ethernet-controller.yaml#
18 - enum:
19 - fsl,imx25-fec
20 - fsl,imx27-fec
21 - fsl,imx28-fec
22 - fsl,imx6q-fec
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| D | mdio.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andrew Lunn <andrew@lunn.ch>
11 - Florian Fainelli <f.fainelli@gmail.com>
12 - Heiner Kallweit <hkallweit1@gmail.com>
17 bus. These should follow the generic ethernet-phy.yaml document, or
24 "#address-cells":
27 "#size-cells":
30 reset-gpios:
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| D | hisilicon-femac.txt | 4 - compatible: should contain one of the following version strings:
5 * "hisilicon,hisi-femac-v1"
6 * "hisilicon,hisi-femac-v2"
7 and the soc string "hisilicon,hi3516cv300-femac".
8 - reg: specifies base physical address(s) and size of the device registers.
11 - interrupts: should contain the MAC interrupt.
12 - clocks: A phandle to the MAC main clock.
13 - resets: should contain the phandle to the MAC reset signal(required) and
15 - reset-names: should contain the reset signal name "mac"(required)
17 - phy-mode: see ethernet.txt [1].
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| /Linux-v5.15/Documentation/devicetree/bindings/input/ |
| D | hid-over-i2c.txt | 1 * HID over I2C Device-Tree bindings
8 http://msdn.microsoft.com/en-us/library/windows/hardware/hh852380.aspx
10 If this binding is used, the kernel module i2c-hid will handle the communication
14 - compatible: must be "hid-over-i2c"
15 - reg: i2c slave address
16 - hid-descr-addr: HID descriptor address
17 - interrupts: interrupt line
23 device-specific compatible properties, which should be used in addition to the
24 "hid-over-i2c" string.
26 - compatible:
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| /Linux-v5.15/drivers/mmc/core/ |
| D | core.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
11 #include <linux/delay.h>
75 void _mmc_detect_change(struct mmc_host *host, unsigned long delay,
125 * mmc_claim_host - exclusively claim a host
140 * mmc_pre_req - Prepare for a new request
150 if (host->ops->pre_req) in mmc_pre_req()
151 host->ops->pre_req(host, mrq); in mmc_pre_req()
155 * mmc_post_req - Post process a completed request
156 * @host: MMC host to post process command
157 * @mrq: MMC request to post process for
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| /Linux-v5.15/drivers/net/ethernet/qlogic/qlcnic/ |
| D | qlcnic_83xx_init.c | 1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright (c) 2009-2013 QLogic Corporation
74 u16 delay; member
78 u16 delay;
136 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE); in qlcnic_83xx_idc_check_driver_presence_reg()
146 cur = adapter->ahw->idc.curr_state; in qlcnic_83xx_idc_log_state_history()
147 prev = adapter->ahw->idc.prev_state; in qlcnic_83xx_idc_log_state_history()
149 dev_info(&adapter->pdev->dev, in qlcnic_83xx_idc_log_state_history()
151 adapter->ahw->idc.name[cur], in qlcnic_83xx_idc_log_state_history()
152 adapter->ahw->idc.name[prev]); in qlcnic_83xx_idc_log_state_history()
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| /Linux-v5.15/drivers/gpu/drm/i915/gt/ |
| D | gen6_engine_cs.c | 1 // SPDX-License-Identifier: MIT
17 * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
21 * [DevSNB-C+{W/A}] Before any depth stall flush (including those
22 * produced by non-pipelined state commands), software needs to first
23 * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
26 * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
27 * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
31 * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
32 * BEFORE the pipe-control with a post-sync op and no write-cache
40 * - Render Target Cache Flush Enable ([12] of DW1)
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| /Linux-v5.15/drivers/spi/ |
| D | spi-imx.c | 1 // SPDX-License-Identifier: GPL-2.0+
2 // Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
7 #include <linux/delay.h>
9 #include <linux/dma-mapping.h>
27 #include <linux/platform_data/dma-imx.h>
128 return d->devtype_data->devtype == IMX27_CSPI; in is_imx27_cspi()
133 return d->devtype_data->devtype == IMX35_CSPI; in is_imx35_cspi()
138 return d->devtype_data->devtype == IMX51_ECSPI; in is_imx51_ecspi()
143 return d->devtype_data->devtype == IMX53_ECSPI; in is_imx53_ecspi()
149 unsigned int val = readl(spi_imx->base + MXC_CSPIRXDATA); \
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| /Linux-v5.15/Documentation/devicetree/bindings/mmc/ |
| D | mmc-pwrseq-simple.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mmc/mmc-pwrseq-simple.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ulf Hansson <ulf.hansson@linaro.org>
19 const: mmc-pwrseq-simple
21 reset-gpios:
28 They will be de-asserted right after the power has been provided to the
33 description: Handle for the entry in clock-names.
35 clock-names:
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| /Linux-v5.15/drivers/clk/tegra/ |
| D | clk.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
9 #include <linux/clk-provider.h>
11 #include <linux/delay.h>
73 * struct tegra_clk_sync_source - external clock source from codec
75 * @hw: handle between common and hardware-specific interfaces
95 * struct tegra_clk_frac_div - fractional divider clock
97 * @hw: handle between common and hardware-specific interfaces
99 * @flags: hardware-specific flags
106 * TEGRA_DIVIDER_ROUND_UP - This flags indicates to round up the divider value.
107 * TEGRA_DIVIDER_FIXED - Fixed rate PLL dividers has addition override bit, this
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| /Linux-v5.15/tools/power/pm-graph/config/ |
| D | suspend-x2-proc.cfg | 2 # Proc S3 (Suspend to Mem) x2 test - includes user processes
9 # sudo ./sleepgraph.py -config config/suspend-proc.cfg
14 # ---- General Options ----
26 output-dir: suspend-{hostname}-{date}-{time}-x2-proc
40 # ---- Advanced Options ----
57 # Back to Back Suspend Delay
58 # Time delay between the two test runs in ms (default: 0 ms)
61 # Pre Suspend Delay
62 # Include an N ms delay before (1st) suspend (default: 0 ms)
65 # Post Resume Delay
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| D | standby-dev.cfg | 2 # Dev S1 (Standby) test - includes src calls / kernel threads
9 # sudo ./sleepgraph.py -config config/standby-dev.cfg
14 # ---- General Options ----
26 output-dir: standby-{hostname}-{date}-{time}-dev
40 # ---- Advanced Options ----
57 # Back to Back Suspend Delay
58 # Time delay between the two test runs in ms (default: 0 ms)
61 # Pre Suspend Delay
62 # Include an N ms delay before (1st) suspend (default: 0 ms)
65 # Post Resume Delay
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| D | freeze-dev.cfg | 2 # Dev S2 (Freeze) test - includes src calls / kernel threads
9 # sudo ./sleepgraph.py -config config/freeze-dev.cfg
14 # ---- General Options ----
26 output-dir: freeze-{hostname}-{date}-{time}-dev
40 # ---- Advanced Options ----
57 # Back to Back Suspend Delay
58 # Time delay between the two test runs in ms (default: 0 ms)
61 # Pre Suspend Delay
62 # Include an N ms delay before (1st) suspend (default: 0 ms)
65 # Post Resume Delay
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| D | suspend-dev.cfg | 2 # Dev S3 (Suspend to Mem) test - includes src calls / kernel threads
9 # sudo ./sleepgraph.py -config config/suspend-dev.cfg
14 # ---- General Options ----
26 output-dir: suspend-{hostname}-{date}-{time}-dev
40 # ---- Advanced Options ----
57 # Back to Back Suspend Delay
58 # Time delay between the two test runs in ms (default: 0 ms)
61 # Pre Suspend Delay
62 # Include an N ms delay before (1st) suspend (default: 0 ms)
65 # Post Resume Delay
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| D | freeze-callgraph.cfg | 9 # sudo ./sleepgraph.py -config config/freeze-callgraph.cfg
15 # ---- General Options ----
27 output-dir: freeze-{hostname}-{date}-{time}-cg
41 # ---- Advanced Options ----
58 # Back to Back Suspend Delay
59 # Time delay between the two test runs in ms (default: 0 ms)
62 # Pre Suspend Delay
63 # Include an N ms delay before (1st) suspend (default: 0 ms)
66 # Post Resume Delay
67 # Include an N ms delay after (last) resume (default: 0 ms)
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| D | standby-callgraph.cfg | 9 # sudo ./sleepgraph.py -config config/standby-callgraph.cfg
15 # ---- General Options ----
27 output-dir: standby-{hostname}-{date}-{time}-cg
41 # ---- Advanced Options ----
58 # Back to Back Suspend Delay
59 # Time delay between the two test runs in ms (default: 0 ms)
62 # Pre Suspend Delay
63 # Include an N ms delay before (1st) suspend (default: 0 ms)
66 # Post Resume Delay
67 # Include an N ms delay after (last) resume (default: 0 ms)
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| D | freeze.cfg | 9 # sudo ./sleepgraph.py -config config/freeze.cfg
14 # ---- General Options ----
26 output-dir: freeze-{hostname}-{date}-{time}
40 # ---- Advanced Options ----
57 # Back to Back Suspend Delay
58 # Time delay between the two test runs in ms (default: 0 ms)
61 # Pre Suspend Delay
62 # Include an N ms delay before (1st) suspend (default: 0 ms)
65 # Post Resume Delay
66 # Include an N ms delay after (last) resume (default: 0 ms)
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| D | standby.cfg | 9 # sudo ./sleepgraph.py -config config/standby.cfg
14 # ---- General Options ----
26 output-dir: standby-{hostname}-{date}-{time}
40 # ---- Advanced Options ----
57 # Back to Back Suspend Delay
58 # Time delay between the two test runs in ms (default: 0 ms)
61 # Pre Suspend Delay
62 # Include an N ms delay before (1st) suspend (default: 0 ms)
65 # Post Resume Delay
66 # Include an N ms delay after (last) resume (default: 0 ms)
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| D | suspend.cfg | 9 # sudo ./sleepgraph.py -config config/suspend.cfg
14 # ---- General Options ----
26 output-dir: suspend-{hostname}-{date}-{time}
40 # ---- Advanced Options ----
57 # Back to Back Suspend Delay
58 # Time delay between the two test runs in ms (default: 0 ms)
61 # Pre Suspend Delay
62 # Include an N ms delay before (1st) suspend (default: 0 ms)
65 # Post Resume Delay
66 # Include an N ms delay after (last) resume (default: 0 ms)
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| D | suspend-callgraph.cfg | 9 # sudo ./sleepgraph.py -config config/suspend.cfg
15 # ---- General Options ----
27 output-dir: suspend-{hostname}-{date}-{time}-cg
41 # ---- Advanced Options ----
58 # Back to Back Suspend Delay
59 # Time delay between the two test runs in ms (default: 0 ms)
62 # Pre Suspend Delay
63 # Include an N ms delay before (1st) suspend (default: 0 ms)
66 # Post Resume Delay
67 # Include an N ms delay after (last) resume (default: 0 ms)
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| /Linux-v5.15/drivers/net/ethernet/emulex/benet/ |
| D | be_hw.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) 2005-2016 Broadcom.
7 * linux-drivers@emulex.com
16 * The software must write this register twice to post any command. First,
33 #define SLIPORT_SEMAPHORE_OFFSET_SH 0x94 /* PCI-CFG offset */
42 /* MPU semphore POST stage values */
44 #define POST_STAGE_HOST_RDY 0x2 /* Host has given go-ahed to FW */
46 #define POST_STAGE_ARMFW_RDY 0xc000 /* FW is done with POST */
127 #define DB_EQ_RING_ID_MASK 0x1FF /* bits 0 - 8 */
128 #define DB_EQ_RING_ID_EXT_MASK 0x3e00 /* bits 9-13 */
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| /Linux-v5.15/drivers/clk/ingenic/ |
| D | cgu.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
5 * Copyright (c) 2013-2015 Imagination Technologies
13 #include <linux/clk-provider.h>
18 * struct ingenic_cgu_pll_info - information about a PLL
33 * @od_shift: the number of bits to shift the post-VCO divider value by (ie.
34 * the index of the lowest bit of the post-VCO divider value in
36 * @od_bits: the size of the post-VCO divider field in bits
37 * @od_max: the maximum post-VCO divider value
38 * @od_encoding: a pointer to an array mapping post-VCO divider values to
39 * their encoded values in the PLL control register, or -1 for
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| /Linux-v5.15/arch/arm64/boot/dts/mediatek/ |
| D | mt8183-kukui-jacuzzi-fennel-sku6.dts | 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
6 /dts-v1/;
7 #include "mt8183-kukui-jacuzzi-fennel.dtsi"
11 compatible = "google,fennel-sku6", "google,fennel", "mediatek,mt8183";
17 compatible = "hid-over-i2c";
19 interrupt-parent = <&pio>;
21 pinctrl-names = "default";
22 pinctrl-0 = <&touchscreen_pins>;
24 post-power-on-delay-ms = <10>;
25 hid-descr-addr = <0x0001>;
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| D | mt8183-kukui-jacuzzi-burnet.dts | 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
6 /dts-v1/;
7 #include "mt8183-kukui-jacuzzi.dtsi"
15 mediatek,dmic-mode = <1>; /* one-wire */
20 compatible = "hid-over-i2c";
22 pinctrl-names = "default";
23 pinctrl-0 = <&touchscreen_pins>;
24 interrupts-extended = <&pio 155 IRQ_TYPE_LEVEL_LOW>;
26 post-power-on-delay-ms = <200>;
27 hid-descr-addr = <0x0020>;
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