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/Linux-v6.1/Documentation/devicetree/bindings/clock/
Drockchip,px30-cru.yaml34 - rockchip,px30-pmucru
48 - description: Clock for both PMUCRU and CRU
49 - description: Clock for CRU (sourced from PMUCRU)
101 pmucru: clock-controller@ff2bc000 {
102 compatible = "rockchip,px30-pmucru";
114 clocks = <&xin24m>, <&pmucru PLL_GPLL>;
Drockchip,rk3568-cru.yaml26 - rockchip,rk3568-pmucru
61 pmucru: clock-controller@fdd00000 {
62 compatible = "rockchip,rk3568-pmucru";
Drockchip,rk3399-cru.yaml36 - rockchip,rk3399-pmucru
71 pmucru: clock-controller@ff750000 {
72 compatible = "rockchip,rk3399-pmucru";
Drockchip,rv1126-cru.yaml22 - rockchip,rv1126-pmucru
/Linux-v6.1/arch/arm64/boot/dts/rockchip/
Drk356x.dtsi411 pmucru: clock-controller@fdd00000 { label
412 compatible = "rockchip,rk3568-pmucru";
425 assigned-clocks = <&cru PLL_GPLL>, <&pmucru PLL_PPLL>;
434 clocks = <&pmucru CLK_I2C0>, <&pmucru PCLK_I2C0>;
447 clocks = <&pmucru SCLK_UART0>, <&pmucru PCLK_UART0>;
460 clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
471 clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
482 clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
493 clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
805 <&pmucru CLK_HDMI_REF>,
[all …]
Drk3568.dtsi54 clocks = <&pmucru CLK_PCIE30PHY_REF_M>, <&pmucru CLK_PCIE30PHY_REF_N>,
217 clocks = <&pmucru CLK_PCIEPHY0_REF>,
221 assigned-clocks = <&pmucru CLK_PCIEPHY0_REF>;
Drk3399.dtsi1199 clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>;
1212 clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>;
1225 assigned-clocks = <&pmucru SCLK_I2C0_PMU>;
1227 clocks = <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>;
1240 assigned-clocks = <&pmucru SCLK_I2C4_PMU>;
1242 clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>;
1255 assigned-clocks = <&pmucru SCLK_I2C8_PMU>;
1257 clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>;
1273 clocks = <&pmucru PCLK_RKPWM_PMU>;
1283 clocks = <&pmucru PCLK_RKPWM_PMU>;
[all …]
Dpx30.dtsi357 clocks = <&pmucru SCLK_UART0_PMU>, <&pmucru PCLK_UART0_PMU>;
806 clocks = <&xin24m>, <&pmucru PLL_GPLL>;
823 pmucru: clock-controller@ff2bc000 { label
824 compatible = "rockchip,px30-pmucru";
833 <&pmucru PLL_GPLL>, <&pmucru PCLK_PMU_PRE>,
834 <&pmucru SCLK_WIFI_PMU>;
850 clocks = <&pmucru SCLK_USBPHY_REF>;
880 clocks = <&pmucru SCLK_MIPIDSIPHY_REF>, <&cru PCLK_MIPIDSIPHY>;
1367 clocks = <&pmucru PCLK_GPIO0_PMU>;
Drk3566-roc-pc.dts614 assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
Drk3568-evb1-v10.dts679 assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
Drk3568-rock-3a.dts716 assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
Drk3566-quartz64-b.dts726 assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
Drk3566-anbernic-rgxx3.dtsi818 assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
Drk3566-quartz64-a.dts826 assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
Drk3568-bpi-r2-pro.dts829 assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
/Linux-v6.1/Documentation/devicetree/bindings/phy/
Drockchip,pcie3-phy.yaml73 clocks = <&pmucru CLK_PCIE30PHY_REF_M>,
74 <&pmucru CLK_PCIE30PHY_REF_N>,
Dphy-rockchip-naneng-combphy.yaml99 clocks = <&pmucru CLK_PCIEPHY0_REF>,
103 assigned-clocks = <&pmucru CLK_PCIEPHY0_REF>;
Drockchip,px30-dsi-dphy.yaml64 clocks = <&pmucru 13>, <&cru 12>;
/Linux-v6.1/include/dt-bindings/clock/
Drk3568-cru.h10 /* pmucru-clocks indices */
12 /* pmucru plls */
16 /* pmucru clocks */
Drockchip,rv1126-cru.h10 /* pmucru-clocks indices */
/Linux-v6.1/drivers/clk/rockchip/
Dclk-rk3399.c1609 CLK_OF_DECLARE(rk3399_cru_pmu, "rockchip,rk3399-pmucru", rk3399_pmu_clk_init);
1628 .compatible = "rockchip,rk3399-pmucru",
Dclk-rk3568.c1636 CLK_OF_DECLARE(rk3568_cru_pmu, "rockchip,rk3568-pmucru", rk3568_pmu_clk_init);
1698 .compatible = "rockchip,rk3568-pmucru",
Dclk-px30.c1068 CLK_OF_DECLARE(px30_cru_pmu, "rockchip,px30-pmucru", px30_pmu_clk_init);
Dclk-rv1126.c1110 .compatible = "rockchip,rv1126-pmucru",