| /Linux-v6.1/Documentation/devicetree/bindings/clock/ |
| D | allwinner,sun4i-a10-pll5-clk.yaml | 4 $id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-pll5-clk.yaml#
23 const: allwinner,sun4i-a10-pll5-clk
47 compatible = "allwinner,sun4i-a10-pll5-clk";
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| D | allwinner,sun4i-a10-mbus-clk.yaml | 50 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
59 clocks = <&osc24M>, <&pll6 1>, <&pll5>;
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| D | allwinner,sun4i-a10-display-clk.yaml | 53 clocks = <&pll3>, <&pll7>, <&pll5 1>;
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| D | allwinner,sun4i-a10-mmc-clk.yaml | 71 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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| D | allwinner,sun4i-a10-mod0-clk.yaml | 67 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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| /Linux-v6.1/drivers/clk/renesas/ |
| D | r8a779f0-cpg-mssr.c | 63 DEF_BASE(".pll5", CLK_PLL5, CLK_TYPE_GEN4_PLL5, CLK_MAIN),
175 * MD EXTAL PLL1 PLL2 PLL3 PLL4 PLL5 PLL6 OSC
187 …/* EXTAL div PLL1 mult/div PLL2 mult/div PLL3 mult/div PLL4 mult/div PLL5 mult/div PLL6 mult/div O…
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| D | r8a779g0-cpg-mssr.c | 74 DEF_BASE(".pll5", CLK_PLL5, CLK_TYPE_GEN4_PLL5, CLK_MAIN),
182 * MD EXTAL PLL1 PLL2 PLL3 PLL4 PLL5 PLL6 OSC
194 …/* EXTAL div PLL1 mult/div PLL2 mult/div PLL3 mult/div PLL4 mult/div PLL5 mult/div PLL6 mult/div O…
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| D | r8a779a0-cpg-mssr.c | 72 DEF_BASE(".pll5", CLK_PLL5, CLK_TYPE_GEN4_PLL5, CLK_MAIN),
245 * MD EXTAL PLL1 PLL20 PLL30 PLL4 PLL5 OSC
256 …/* EXTAL div PLL1 mult/div PLL2 mult/div PLL3 mult/div PLL4 mult/div PLL5 mult/div PLL6 mult/div O…
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| D | rzg2l-cpg.c | 98 * @pll5_mux_dsi_div_params: pll5 mux and dsi div parameters
575 * OSC --> PLL5 --> FOUTPOSTDIV-->| in rzg2l_cpg_sipll5_set_rate()
580 * rate and the pll5 parameters for generating FOUTPOSTDIV. It propagates in rzg2l_cpg_sipll5_set_rate()
583 * OSC --> PLL5 --> FOUTPOSTDIV in rzg2l_cpg_sipll5_set_rate()
593 /* Put PLL5 into standby mode */ in rzg2l_cpg_sipll5_set_rate()
598 dev_err(priv->dev, "failed to release pll5 lock"); in rzg2l_cpg_sipll5_set_rate()
627 dev_err(priv->dev, "failed to lock pll5"); in rzg2l_cpg_sipll5_set_rate()
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| D | r9a07g043-cpg.c | 106 DEF_FIXED(".pll5", CLK_PLL5, CLK_EXTAL, 125, 1),
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| D | r9a07g044-cpg.c | 121 DEF_FIXED(".pll5", CLK_PLL5, CLK_EXTAL, 125, 1),
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| /Linux-v6.1/Documentation/devicetree/bindings/mips/ |
| D | mscc.txt | 48 configuration and status of PLL5, RCOMP, SyncE, SerDes configurations and
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| /Linux-v6.1/drivers/clk/mmp/ |
| D | clk-of-pxa1928.c | 38 {0, "pll5", NULL, 0, 1248000000},
143 static const char *sdh_parent_names[] = {"pll1_624", "pll5p", "pll5", "pll1_416"};
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| /Linux-v6.1/drivers/clk/sunxi/ |
| D | clk-sunxi.c | 195 * sun4i_get_pll5_factors() - calculates n, k factors for PLL5
196 * PLL5 rate is calculated as follows
1017 clkflags = !strcmp("pll5", parent) ? 0 : CLK_SET_RATE_PARENT; in sunxi_divs_clk_setup()
1114 CLK_OF_DECLARE(sun4i_pll5, "allwinner,sun4i-a10-pll5-clk",
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| D | clk-factors.c | 195 * some factor clocks, such as pll5 and pll6, may have multiple in __sunxi_factors_register()
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| /Linux-v6.1/include/dt-bindings/clock/ |
| D | qcom,gcc-msm8660.h | 258 #define PLL5 249 macro
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| D | qcom,gcc-mdm9615.h | 291 #define PLL5 281 macro
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| D | qcom,gcc-msm8960.h | 289 #define PLL5 281 macro
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| /Linux-v6.1/drivers/clk/imx/ |
| D | clk-imx6sl.c | 68 static const char *pll5_bypass_sels[] = { "pll5", "pll5_bypass_src", };
221 hws[IMX6SL_CLK_PLL5] = imx_clk_hw_pllv3(IMX_PLLV3_AV, "pll5", "osc", base + 0xa0, 0x7f); in imx6sl_clocks_init()
436 /* set PLL5 video as lcdif pix parent clock */ in imx6sl_clocks_init()
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| D | clk-imx6sll.c | 27 static const char *pll5_bypass_sels[] = { "pll5", "pll5_bypass_src", };
127 …hws[IMX6SLL_CLK_PLL5] = imx_clk_hw_pllv3(IMX_PLLV3_AV, "pll5", "pll5_bypass_src", base + 0xa0, 0x… in imx6sll_clocks_init()
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| D | clk-vf610.c | 81 static const char *pll5_bypass_sels[] = { "pll5", "pll5_bypass_src", };
223 clk[VF610_CLK_PLL5] = imx_clk_pllv3(IMX_PLLV3_ENET, "pll5", "pll5_bypass_src", PLL5_CTRL, 0x3); in vf610_clocks_init()
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| D | clk-imx6ul.c | 25 static const char *pll5_bypass_sels[] = { "pll5", "pll5_bypass_src", };
153 hws[IMX6UL_CLK_PLL5] = imx_clk_hw_pllv3(IMX_PLLV3_AV, "pll5", "osc", base + 0xa0, 0x7f); in imx6ul_clocks_init()
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| D | clk-imx6q.c | 88 static const char *pll5_bypass_sels[] = { "pll5", "pll5_bypass_src", };
410 /* Make sure PLL5 is disabled */ in disable_anatop_clocks()
481 hws[IMX6QDL_CLK_PLL5] = imx_clk_hw_pllv3(IMX_PLLV3_AV, "pll5", "osc", base + 0xa0, 0x7f); in imx6q_clocks_init()
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| D | clk-imx6sx.c | 81 static const char *pll5_bypass_sels[] = { "pll5", "pll5_bypass_src", };
164 hws[IMX6SX_CLK_PLL5] = imx_clk_hw_pllv3(IMX_PLLV3_AV, "pll5", "osc", base + 0xa0, 0x7f); in imx6sx_clocks_init()
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| /Linux-v6.1/drivers/net/ethernet/mscc/ |
| D | ocelot_vsc7514.c | 109 /* Configure PLL5. This will need a proper CCF driver in ocelot_pll5_init()
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