| /Linux-v5.10/Documentation/devicetree/bindings/clock/ |
| D | allwinner,sun4i-a10-pll5-clk.yaml | 4 $id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-pll5-clk.yaml#
23 const: allwinner,sun4i-a10-pll5-clk
47 compatible = "allwinner,sun4i-a10-pll5-clk";
|
| D | allwinner,sun4i-a10-mbus-clk.yaml | 50 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
59 clocks = <&osc24M>, <&pll6 1>, <&pll5>;
|
| D | allwinner,sun4i-a10-display-clk.yaml | 53 clocks = <&pll3>, <&pll7>, <&pll5 1>;
|
| D | allwinner,sun4i-a10-mmc-clk.yaml | 71 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
|
| D | allwinner,sun4i-a10-mod0-clk.yaml | 67 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
|
| /Linux-v5.10/drivers/clk/renesas/ |
| D | r8a779a0-cpg-mssr.c | 95 DEF_BASE(".pll5", CLK_PLL5, CLK_TYPE_R8A779A0_PLL5, CLK_MAIN),
225 * MD EXTAL PLL1 PLL20 PLL30 PLL4 PLL5 OSC
237 /* EXTAL div PLL1 mult/div PLL5 mult/div OSC prediv */
|
| /Linux-v5.10/Documentation/devicetree/bindings/mips/ |
| D | mscc.txt | 48 configuration and status of PLL5, RCOMP, SyncE, SerDes configurations and
|
| /Linux-v5.10/drivers/clk/mmp/ |
| D | clk-of-pxa1928.c | 41 {0, "pll5", NULL, 0, 1248000000},
146 static const char *sdh_parent_names[] = {"pll1_624", "pll5p", "pll5", "pll1_416"};
|
| /Linux-v5.10/drivers/clk/sunxi/ |
| D | clk-sunxi.c | 195 * sun4i_get_pll5_factors() - calculates n, k factors for PLL5
196 * PLL5 rate is calculated as follows
1017 clkflags = !strcmp("pll5", parent) ? 0 : CLK_SET_RATE_PARENT; in sunxi_divs_clk_setup()
1114 CLK_OF_DECLARE(sun4i_pll5, "allwinner,sun4i-a10-pll5-clk",
|
| D | clk-factors.c | 195 * some factor clocks, such as pll5 and pll6, may have multiple in __sunxi_factors_register()
|
| /Linux-v5.10/include/dt-bindings/clock/ |
| D | qcom,gcc-msm8660.h | 258 #define PLL5 249 macro
|
| D | qcom,gcc-mdm9615.h | 291 #define PLL5 281 macro
|
| D | qcom,gcc-msm8960.h | 289 #define PLL5 281 macro
|
| /Linux-v5.10/drivers/clk/imx/ |
| D | clk-imx6sl.c | 67 static const char *pll5_bypass_sels[] = { "pll5", "pll5_bypass_src", };
228 hws[IMX6SL_CLK_PLL5] = imx_clk_hw_pllv3(IMX_PLLV3_AV, "pll5", "osc", base + 0xa0, 0x7f); in imx6sl_clocks_init()
443 /* set PLL5 video as lcdif pix parent clock */ in imx6sl_clocks_init()
|
| D | clk-imx6sll.c | 27 static const char *pll5_bypass_sels[] = { "pll5", "pll5_bypass_src", };
143 …hws[IMX6SLL_CLK_PLL5] = imx_clk_hw_pllv3(IMX_PLLV3_AV, "pll5", "pll5_bypass_src", base + 0xa0, 0x… in imx6sll_clocks_init()
|
| D | clk-vf610.c | 81 static const char *pll5_bypass_sels[] = { "pll5", "pll5_bypass_src", };
223 clk[VF610_CLK_PLL5] = imx_clk_pllv3(IMX_PLLV3_ENET, "pll5", "pll5_bypass_src", PLL5_CTRL, 0x3); in vf610_clocks_init()
|
| D | clk-imx6ul.c | 25 static const char *pll5_bypass_sels[] = { "pll5", "pll5_bypass_src", };
153 hws[IMX6UL_CLK_PLL5] = imx_clk_hw_pllv3(IMX_PLLV3_AV, "pll5", "osc", base + 0xa0, 0x7f); in imx6ul_clocks_init()
|
| D | clk-imx6q.c | 88 static const char *pll5_bypass_sels[] = { "pll5", "pll5_bypass_src", };
417 /* Make sure PLL5 is disabled */ in disable_anatop_clocks()
489 hws[IMX6QDL_CLK_PLL5] = imx_clk_hw_pllv3(IMX_PLLV3_AV, "pll5", "osc", base + 0xa0, 0x7f); in imx6q_clocks_init()
|
| D | clk-imx6sx.c | 81 static const char *pll5_bypass_sels[] = { "pll5", "pll5_bypass_src", };
172 hws[IMX6SX_CLK_PLL5] = imx_clk_hw_pllv3(IMX_PLLV3_AV, "pll5", "osc", base + 0xa0, 0x7f); in imx6sx_clocks_init()
|
| /Linux-v5.10/sound/soc/codecs/ |
| D | wm8804.c | 41 { 7, 0x16 }, /* R7 - PLL5 */
|
| /Linux-v5.10/drivers/net/ethernet/mscc/ |
| D | ocelot_vsc7514.c | 486 /* Configure PLL5. This will need a proper CCF driver in ocelot_pll5_init()
|
| /Linux-v5.10/drivers/ptp/ |
| D | ptp_clockmatrix.c | 391 /* PLL5 can have OUT8 as second additional output. */ in _sync_pll_output()
|
| /Linux-v5.10/drivers/misc/habanalabs/include/gaudi/ |
| D | gaudi_async_ids_map_extended.h | 270 { .fc_id = 244, .cpu_id = 119, .valid = 1, .name = "PLL5" },
|
