| /Linux-v6.1/Documentation/devicetree/bindings/clock/ |
| D | allwinner,sun9i-a80-pll4-clk.yaml | 4 $id: http://devicetree.org/schemas/clock/allwinner,sun9i-a80-pll4-clk.yaml#
20 const: allwinner,sun9i-a80-pll4-clk
44 compatible = "allwinner,sun9i-a80-pll4-clk";
47 clock-output-names = "pll4";
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| D | allwinner,sun9i-a80-apb0-clk.yaml | 50 clocks = <&osc24M>, <&pll4>;
59 clocks = <&osc24M>, <&pll4>;
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| D | allwinner,sun4i-a10-ve-clk.yaml | 51 clocks = <&pll4>;
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| D | allwinner,sun9i-a80-cpus-clk.yaml | 48 clocks = <&osc32k>, <&osc24M>, <&pll4>, <&pll3>;
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| D | allwinner,sun9i-a80-gt-clk.yaml | 48 clocks = <&osc24M>, <&pll4>, <&pll12>, <&pll12>;
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| D | allwinner,sun9i-a80-ahb-clk.yaml | 48 clocks = <>_clk>, <&pll4>, <&pll12>, <&pll12>;
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| D | allwinner,sun4i-a10-mmc-clk.yaml | 82 clocks = <&osc24M>, <&pll4>;
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| D | qcom,gcc-apq8064.yaml | 48 - const: pll4
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| /Linux-v6.1/drivers/clk/qcom/ |
| D | lcc-ipq806x.c | 27 static struct clk_pll pll4 = { variable
36 .name = "pll4",
402 [PLL4] = &pll4.clkr,
451 /* Configure the rate of PLL4 if the bootloader hasn't already */ in lcc_ipq806x_probe()
454 clk_pll_configure_sr(&pll4, regmap, &pll4_config, true); in lcc_ipq806x_probe()
455 /* Enable PLL4 source on the LPASS Primary PLL Mux */ in lcc_ipq806x_probe()
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| D | lcc-mdm9615.c | 28 static struct clk_pll pll4 = { variable
37 .name = "pll4",
481 [PLL4] = &pll4.clkr,
544 /* Use the correct frequency plan depending on speed of PLL4 */ in lcc_mdm9615_probe()
555 /* Enable PLL4 source on the LPASS Primary PLL Mux */ in lcc_mdm9615_probe()
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| D | lcc-msm8960.c | 26 static struct clk_pll pll4 = { variable
35 .name = "pll4",
396 [PLL4] = &pll4.clkr,
460 /* Use the correct frequency plan depending on speed of PLL4 */ in lcc_msm8960_probe()
471 /* Enable PLL4 source on the LPASS Primary PLL Mux */ in lcc_msm8960_probe()
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| /Linux-v6.1/Documentation/devicetree/bindings/sound/ |
| D | ti,j721e-cpb-audio.yaml | 19 clock for AUDIO_REFCLK2 needs to be changed between PLL4 (for 48KHz) and
25 PLL4 ---> PLL4_HSDIV0 ---> MCASP10_AUXCLK ---> McASP10.auxclk
34 PLL4 ---> PLL4_HSDIV0 ---> MCASP0_AUXCLK ---> McASP0.auxclk
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| D | ti,j721e-cpb-ivi-audio.yaml | 24 for AUDIO_REFCLK0 needs to be changed between PLL4 (for 48KHz) and PLL15 (for
28 Note: the same PLL4 and PLL15 is used by the audio support on the CPB!
31 PLL4 ---> PLL4_HSDIV0 ---> MCASP10_AUXCLK ---> McASP10.auxclk
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| /Linux-v6.1/drivers/clk/sunxi/ |
| D | clk-sun9i-core.c | 18 * sun9i_a80_get_pll4_factors() - calculates n, p, m factors for PLL4
19 * PLL4 rate is calculated as follows
82 pr_err("Could not get registers for a80-pll4-clk: %pOFn\n", in sun9i_a80_pll4_setup()
90 CLK_OF_DECLARE(sun9i_a80_pll4, "allwinner,sun9i-a80-pll4-clk", sun9i_a80_pll4_setup);
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| D | clk-sun9i-cpus.c | 62 /* apply pre-divider first if parent is pll4 */ in sun9i_a80_cpus_clk_recalc_rate()
86 /* calculate pre-divider if parent is pll4 */ in sun9i_a80_cpus_clk_round()
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| /Linux-v6.1/drivers/clk/renesas/ |
| D | r8a779g0-cpg-mssr.c | 73 DEF_BASE(".pll4", CLK_PLL4, CLK_TYPE_GEN4_PLL4, CLK_MAIN),
182 * MD EXTAL PLL1 PLL2 PLL3 PLL4 PLL5 PLL6 OSC
194 …/* EXTAL div PLL1 mult/div PLL2 mult/div PLL3 mult/div PLL4 mult/div PLL5 mult/div PLL6 mult/div O…
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| D | r8a779f0-cpg-mssr.c | 175 * MD EXTAL PLL1 PLL2 PLL3 PLL4 PLL5 PLL6 OSC
187 …/* EXTAL div PLL1 mult/div PLL2 mult/div PLL3 mult/div PLL4 mult/div PLL5 mult/div PLL6 mult/div O…
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| D | r8a779a0-cpg-mssr.c | 245 * MD EXTAL PLL1 PLL20 PLL30 PLL4 PLL5 OSC
256 …/* EXTAL div PLL1 mult/div PLL2 mult/div PLL3 mult/div PLL4 mult/div PLL5 mult/div PLL6 mult/div O…
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| /Linux-v6.1/include/dt-bindings/clock/ |
| D | qcom,lcc-ipq806x.h | 9 #define PLL4 0 macro
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| D | qcom,lcc-msm8960.h | 9 #define PLL4 0 macro
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| D | qcom,lcc-mdm9615.h | 11 #define PLL4 0 macro
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| /Linux-v6.1/drivers/clk/imx/ |
| D | clk-imx8ulp.c | 37 static const char * const hifi_sels[] = { "frosc", "pll4", "pll4_pfd0", "sosc",
40 "pll4", "pll4", "pll4", "pll4", };
251 clks[IMX8ULP_CLK_PLL4] = imx_clk_hw_pllv4(IMX_PLLV4_IMX8ULP, "pll4", "pll4_pre_sel", base + 0x600); in imx8ulp_clk_cgc2_init()
252 clks[IMX8ULP_CLK_PLL4_VCODIV] = imx_clk_hw_divider("pll4_vcodiv", "pll4", base + 0x604, 0, 6); in imx8ulp_clk_cgc2_init()
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| /Linux-v6.1/arch/arm/boot/dts/ |
| D | stm32mp157c-odyssey.dts | 41 assigned-clock-rates = <125000000>; /* Clock PLL4 to 750Mhz in ATF/U-Boot */
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| D | qcom-msm8960.dtsi | 136 <&lcc PLL4>;
137 clock-names = "cxo", "pxo", "pll4";
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| /Linux-v6.1/sound/soc/ti/ |
| D | j721e-evm.c | 207 clk_id == J721E_CLK_PARENT_48000 ? "PLL4" : "PLL15", in j721e_configure_refclk()
520 [J721E_CLK_PARENT_48000] = 1179648000, /* PLL4 */
529 [J721E_CLK_PARENT_48000] = 1179648000, /* PLL4 */
537 [J721E_CLK_PARENT_48000] = 2359296000u, /* PLL4 */
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