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/Linux-v5.10/Documentation/devicetree/bindings/clock/
Dallwinner,sun9i-a80-pll4-clk.yaml4 $id: http://devicetree.org/schemas/clock/allwinner,sun9i-a80-pll4-clk.yaml#
20 const: allwinner,sun9i-a80-pll4-clk
44 compatible = "allwinner,sun9i-a80-pll4-clk";
47 clock-output-names = "pll4";
Dallwinner,sun9i-a80-apb0-clk.yaml50 clocks = <&osc24M>, <&pll4>;
59 clocks = <&osc24M>, <&pll4>;
Dallwinner,sun4i-a10-ve-clk.yaml51 clocks = <&pll4>;
Dallwinner,sun9i-a80-ahb-clk.yaml48 clocks = <&gt_clk>, <&pll4>, <&pll12>, <&pll12>;
Dallwinner,sun9i-a80-cpus-clk.yaml48 clocks = <&osc32k>, <&osc24M>, <&pll4>, <&pll3>;
Dallwinner,sun9i-a80-gt-clk.yaml48 clocks = <&osc24M>, <&pll4>, <&pll12>, <&pll12>;
Dallwinner,sun4i-a10-mmc-clk.yaml82 clocks = <&osc24M>, <&pll4>;
/Linux-v5.10/drivers/clk/qcom/
Dlcc-ipq806x.c26 static struct clk_pll pll4 = { variable
35 .name = "pll4",
394 [PLL4] = &pll4.clkr,
437 /* Configure the rate of PLL4 if the bootloader hasn't already */ in lcc_ipq806x_probe()
440 clk_pll_configure_sr(&pll4, regmap, &pll4_config, true); in lcc_ipq806x_probe()
441 /* Enable PLL4 source on the LPASS Primary PLL Mux */ in lcc_ipq806x_probe()
Dlcc-mdm9615.c28 static struct clk_pll pll4 = { variable
37 .name = "pll4",
481 [PLL4] = &pll4.clkr,
544 /* Use the correct frequency plan depending on speed of PLL4 */ in lcc_mdm9615_probe()
555 /* Enable PLL4 source on the LPASS Primary PLL Mux */ in lcc_mdm9615_probe()
Dlcc-msm8960.c26 static struct clk_pll pll4 = { variable
35 .name = "pll4",
479 [PLL4] = &pll4.clkr,
543 /* Use the correct frequency plan depending on speed of PLL4 */ in lcc_msm8960_probe()
554 /* Enable PLL4 source on the LPASS Primary PLL Mux */ in lcc_msm8960_probe()
/Linux-v5.10/Documentation/devicetree/bindings/sound/
Dti,j721e-cpb-audio.yaml17 clock for AUDIO_REFCLK2 needs to be changed between PLL4 (for 48KHz) and
23 PLL4 ---> PLL4_HSDIV0 ---> MCASP10_AUXCLK ---> McASP10.auxclk
32 PLL4 ---> PLL4_HSDIV0 ---> MCASP0_AUXCLK ---> McASP0.auxclk
Dti,j721e-cpb-ivi-audio.yaml22 for AUDIO_REFCLK0 needs to be changed between PLL4 (for 48KHz) and PLL15 (for
26 Note: the same PLL4 and PLL15 is used by the audio support on the CPB!
29 PLL4 ---> PLL4_HSDIV0 ---> MCASP10_AUXCLK ---> McASP10.auxclk
/Linux-v5.10/drivers/clk/sunxi/
Dclk-sun9i-core.c18 * sun9i_a80_get_pll4_factors() - calculates n, p, m factors for PLL4
19 * PLL4 rate is calculated as follows
82 pr_err("Could not get registers for a80-pll4-clk: %pOFn\n", in sun9i_a80_pll4_setup()
90 CLK_OF_DECLARE(sun9i_a80_pll4, "allwinner,sun9i-a80-pll4-clk", sun9i_a80_pll4_setup);
Dclk-sun9i-cpus.c62 /* apply pre-divider first if parent is pll4 */ in sun9i_a80_cpus_clk_recalc_rate()
86 /* calculate pre-divider if parent is pll4 */ in sun9i_a80_cpus_clk_round()
/Linux-v5.10/include/dt-bindings/clock/
Dqcom,lcc-ipq806x.h9 #define PLL4 0 macro
Dqcom,lcc-msm8960.h9 #define PLL4 0 macro
Dqcom,lcc-mdm9615.h11 #define PLL4 0 macro
Dstm32mp1-clks.h186 #define PLL4 179 macro
/Linux-v5.10/arch/arm/boot/dts/
Dstm32mp157c-odyssey.dts35 assigned-clock-rates = <125000000>; /* Clock PLL4 to 750Mhz in ATF/U-Boot */
/Linux-v5.10/sound/soc/ti/
Dj721e-evm.c205 clk_id == J721E_CLK_PARENT_48000 ? "PLL4" : "PLL15", in j721e_configure_refclk()
515 [J721E_CLK_PARENT_48000] = 1179648000, /* PLL4 */
524 [J721E_CLK_PARENT_48000] = 1179648000, /* PLL4 */
532 [J721E_CLK_PARENT_48000] = 2359296000u, /* PLL4 */
/Linux-v5.10/drivers/clk/renesas/
Dr8a774a1-cpg-mssr.c61 DEF_BASE(".pll4", CLK_PLL4, CLK_TYPE_GEN3_PLL4, CLK_MAIN),
249 * MD EXTAL PLL0 PLL1 PLL2 PLL3 PLL4 OSC
Dr8a774b1-cpg-mssr.c59 DEF_BASE(".pll4", CLK_PLL4, CLK_TYPE_GEN3_PLL4, CLK_MAIN),
245 * MD EXTAL PLL0 PLL1 PLL3 PLL4 OSC
Dr8a77965-cpg-mssr.c63 DEF_BASE(".pll4", CLK_PLL4, CLK_TYPE_GEN3_PLL4, CLK_MAIN),
275 * MD EXTAL PLL0 PLL1 PLL3 PLL4 OSC
Dr8a774e1-cpg-mssr.c62 DEF_BASE(".pll4", CLK_PLL4, CLK_TYPE_GEN3_PLL4, CLK_MAIN),
266 * MD EXTAL PLL0 PLL1 PLL2 PLL3 PLL4 OSC
Dr8a7796-cpg-mssr.c67 DEF_BASE(".pll4", CLK_PLL4, CLK_TYPE_GEN3_PLL4, CLK_MAIN),
274 * MD EXTAL PLL0 PLL1 PLL2 PLL3 PLL4 OSC

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