| /Linux-v5.10/Documentation/devicetree/bindings/clock/ |
| D | allwinner,sun4i-a10-pll3-clk.yaml | 4 $id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-pll3-clk.yaml#
20 const: allwinner,sun4i-a10-pll3-clk
44 compatible = "allwinner,sun4i-a10-pll3-clk";
47 clock-output-names = "pll3";
|
| D | allwinner,sun4i-a10-tcon-ch0-clk.yaml | 64 clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>;
73 clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>;
|
| D | allwinner,sun9i-a80-cpus-clk.yaml | 48 clocks = <&osc32k>, <&osc24M>, <&pll4>, <&pll3>;
|
| D | fixed-factor-clock.yaml | 16 - allwinner,sun4i-a10-pll3-2x-clk
|
| D | allwinner,sun4i-a10-display-clk.yaml | 53 clocks = <&pll3>, <&pll7>, <&pll5 1>;
|
| D | prima2-clock.txt | 19 pll3 4
|
| /Linux-v5.10/sound/soc/codecs/ |
| D | ak4642.c | 113 #define PLL3 (1 << 7) macro
117 #define PLL_MASK (PLL3 | PLL2 | PLL1 | PLL0)
357 pll = PLL3 | PLL2; in ak4642_dai_set_sysclk()
360 pll = PLL3 | PLL2 | PLL0; in ak4642_dai_set_sysclk()
363 pll = PLL3; in ak4642_dai_set_sysclk()
367 pll = PLL3 | PLL2 | PLL1; in ak4642_dai_set_sysclk()
371 pll = PLL3 | PLL2 | PLL1 | PLL0; in ak4642_dai_set_sysclk()
|
| /Linux-v5.10/drivers/clk/renesas/ |
| D | r8a77470-cpg-mssr.c | 46 DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN2_PLL3, CLK_MAIN),
173 * MD EXTAL PLL0 PLL1 PLL3
188 /* EXTAL div PLL1 mult x2 PLL3 mult */
|
| D | r8a77980-cpg-mssr.c | 60 DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN),
192 * MD EXTAL PLL2 PLL1 PLL3 OSC
204 /* EXTAL div PLL1 mult/div PLL3 mult/div OSC prediv */
|
| D | r8a77995-cpg-mssr.c | 59 DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN),
195 * MD19 EXTAL (MHz) PLL0 PLL1 PLL3
203 /* EXTAL div PLL1 mult/div PLL3 mult/div */
|
| D | r8a7745-cpg-mssr.c | 46 DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN2_PLL3, CLK_MAIN),
190 * MD EXTAL PLL0 PLL1 PLL3
205 /* EXTAL div PLL1 mult PLL3 mult PLL0 mult */
|
| D | r8a77970-cpg-mssr.c | 73 DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN),
177 * MD EXTAL PLL0 PLL1 PLL3
194 /* EXTAL div PLL1 mult/div PLL3 mult/div */
|
| D | r8a7742-cpg-mssr.c | 46 DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN2_PLL3, CLK_MAIN),
212 * MD EXTAL PLL0 PLL1 PLL3
231 /* EXTAL div PLL1 mult PLL3 mult */
|
| D | r8a7743-cpg-mssr.c | 47 DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN2_PLL3, CLK_MAIN),
206 * MD EXTAL PLL0 PLL1 PLL3
225 /* EXTAL div PLL1 mult PLL3 mult */
|
| D | r8a774c0-cpg-mssr.c | 61 DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN),
250 * MD19 EXTAL (MHz) PLL0 PLL1 PLL3
258 /* EXTAL div PLL1 mult/div PLL3 mult/div */
|
| D | r8a77990-cpg-mssr.c | 61 DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN),
257 * MD19 EXTAL (MHz) PLL0 PLL1 PLL3
265 /* EXTAL div PLL1 mult/div PLL3 mult/div */
|
| D | r8a774a1-cpg-mssr.c | 60 DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN),
249 * MD EXTAL PLL0 PLL1 PLL2 PLL3 PLL4 OSC
275 /* EXTAL div PLL1 mult/div PLL3 mult/div OSC prediv */
|
| D | r8a774b1-cpg-mssr.c | 58 DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN),
245 * MD EXTAL PLL0 PLL1 PLL3 PLL4 OSC
271 /* EXTAL div PLL1 mult/div PLL3 mult/div OSC prediv */
|
| D | r8a77965-cpg-mssr.c | 62 DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN),
275 * MD EXTAL PLL0 PLL1 PLL3 PLL4 OSC
301 /* EXTAL div PLL1 mult/div PLL3 mult/div OSC prediv */
|
| D | r8a774e1-cpg-mssr.c | 61 DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN),
266 * MD EXTAL PLL0 PLL1 PLL2 PLL3 PLL4 OSC
292 /* EXTAL div PLL1 mult/div PLL3 mult/div OSC prediv */
|
| D | r8a7796-cpg-mssr.c | 66 DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN),
274 * MD EXTAL PLL0 PLL1 PLL2 PLL3 PLL4 OSC
300 /* EXTAL div PLL1 mult/div PLL3 mult/div OSC prediv */
|
| D | r8a7792-cpg-mssr.c | 48 DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN2_PLL3, CLK_MAIN),
164 * MD EXTAL PLL0 PLL1 PLL3
|
| /Linux-v5.10/drivers/clk/sirf/ |
| D | clk-common.c | 21 * - 3 standard configurable plls: pll1, pll2 & pll3
26 * X_XIN, X_XINW, PLL1, PLL2 and PLL3. The domain clock is used as the source
211 .name = "pll3",
293 "pll3",
302 /* parent of io domain can only be pll3 */ in dmn_clk_get_parent()
317 /* parent of io domain can only be pll3 */ in dmn_clk_set_parent()
|
| /Linux-v5.10/drivers/clk/sunxi/ |
| D | Makefile | 18 obj-$(CONFIG_CLK_SUNXI_CLOCKS) += clk-sun4i-pll3.o
|
| D | clk-sun4i-pll3.c | 89 CLK_OF_DECLARE(sun4i_a10_pll3, "allwinner,sun4i-a10-pll3-clk",
|
