| /Linux-v5.10/Documentation/devicetree/bindings/clock/ti/davinci/ |
| D | pll.txt | 9 - "ti,da850-pll0" for PLL0 on DA850/OMAP-L138/AM18XX
14 - for "ti,da850-pll0", shall be "clksrc", "extclksrc"
20 This property is only valid when compatible = "ti,da850-pll0".
42 This child node is only valid when compatible = "ti,da850-pll0".
56 pll0: clock-controller@11000 {
57 compatible = "ti,da850-pll0";
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| /Linux-v5.10/Documentation/devicetree/bindings/clock/ |
| D | qoriq-clock.txt | 159 pll0: pll0@800 {
164 clock-output-names = "pll0", "pll0-div2";
179 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
180 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
188 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
189 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
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| D | silabs,si5351.txt | 82 /* connect xtal input as source of pll0 and pll1 */
88 * - pll0 as clock source of multisynth0
90 * - multisynth0 can change pll0
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| D | renesas,cpg-clocks.yaml | 74 - const: pll0
200 - const: pll0
|
| /Linux-v5.10/drivers/clk/mxs/ |
| D | clk-imx28.c | 127 static const char *const sel_pll0[] __initconst = { "pll0", "ref_xtal", };
130 static const char *const ptp_sels[] __initconst = { "ref_xtal", "pll0", };
133 ref_xtal, pll0, pll1, pll2, ref_cpu, ref_emi, ref_io0, ref_io1, enumerator
168 clks[pll0] = mxs_clk_pll("pll0", "ref_xtal", PLL0CTRL0, 17, 480000000); in mx28_clocks_init()
171 clks[ref_cpu] = mxs_clk_ref("ref_cpu", "pll0", FRAC0, 0); in mx28_clocks_init()
172 clks[ref_emi] = mxs_clk_ref("ref_emi", "pll0", FRAC0, 1); in mx28_clocks_init()
173 clks[ref_io1] = mxs_clk_ref("ref_io1", "pll0", FRAC0, 2); in mx28_clocks_init()
174 clks[ref_io0] = mxs_clk_ref("ref_io0", "pll0", FRAC0, 3); in mx28_clocks_init()
175 clks[ref_pix] = mxs_clk_ref("ref_pix", "pll0", FRAC1, 0); in mx28_clocks_init()
176 clks[ref_hsadc] = mxs_clk_ref("ref_hsadc", "pll0", FRAC1, 1); in mx28_clocks_init()
[all …]
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| /Linux-v5.10/drivers/clk/mvebu/ |
| D | cp110-system-controller.c | 14 * - PLL0 (1 Ghz)
15 * - PPv2 core (1/3 PLL0)
16 * - x2 Core (1/2 PLL0)
18 * - SDIO (2/5 PLL0)
22 * - 2/5 PLL0
247 /* Register the PLL0 which is the root of the hw tree */ in cp110_syscon_common_probe()
248 pll0_name = ap_cp_unique_name(dev, syscon_node, "pll0"); in cp110_syscon_common_probe()
258 /* PPv2 is PLL0/3 */ in cp110_syscon_common_probe()
268 /* X2CORE clock is PLL0/2 */ in cp110_syscon_common_probe()
289 /* NAND can be either PLL0/2.5 or core clock */ in cp110_syscon_common_probe()
[all …]
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| /Linux-v5.10/drivers/bcma/ |
| D | driver_chipcommon_pmu.c | 84 u32 pll0, mask; in bcma_pmu2_pll_init0() local
115 pll0 = bcma_chipco_pll_read(cc, BCMA_CC_PMU15_PLL_PLLCTL0); in bcma_pmu2_pll_init0()
116 freq_tgt_current = (pll0 & BCMA_CC_PMU15_PLL_PC0_FREQTGT_MASK) >> in bcma_pmu2_pll_init0()
137 pll0 &= ~BCMA_CC_PMU15_PLL_PC0_FREQTGT_MASK; in bcma_pmu2_pll_init0()
138 pll0 |= freq_tgt_target << BCMA_CC_PMU15_PLL_PC0_FREQTGT_SHIFT; in bcma_pmu2_pll_init0()
139 bcma_chipco_pll_write(cc, BCMA_CC_PMU15_PLL_PLLCTL0, pll0); in bcma_pmu2_pll_init0()
351 * pllreg "pll0" i.e. 12 for main 6 for phy, 0 for misc.
353 static u32 bcma_pmu_pll_clock(struct bcma_drv_cc *cc, u32 pll0, u32 m) in bcma_pmu_pll_clock() argument
358 BUG_ON((pll0 & 3) || (pll0 > BCMA_CC_PMU4716_MAINPLL_PLL0)); in bcma_pmu_pll_clock()
370 tmp = bcma_chipco_pll_read(cc, pll0 + BCMA_CC_PPL_P1P2_OFF); in bcma_pmu_pll_clock()
[all …]
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| /Linux-v5.10/drivers/soc/kendryte/ |
| D | k210-sysctl.c | 136 u32 clksel0, pll0; in k210_sysctl_clk_recalc_rate() local
141 * Otherwise, use PLL0 frequency with a frequency divisor. in k210_sysctl_clk_recalc_rate()
148 * Get PLL0 frequency: in k210_sysctl_clk_recalc_rate()
151 pll0 = readl(s->regs + K210_SYSCTL_PLL0); in k210_sysctl_clk_recalc_rate()
152 clkr0 = 1 + FIELD_GET(GENMASK(3, 0), pll0); in k210_sysctl_clk_recalc_rate()
153 clkf0 = 1 + FIELD_GET(GENMASK(9, 4), pll0); in k210_sysctl_clk_recalc_rate()
154 clkod0 = 1 + FIELD_GET(GENMASK(13, 10), pll0); in k210_sysctl_clk_recalc_rate()
|
| /Linux-v5.10/include/linux/firmware/imx/svc/ |
| D | pm.h | 80 #define IMX_SC_PM_PARENT_PLL0 1 /* Parent is PLL0 */
81 #define IMX_SC_PM_PARENT_PLL1 2 /* Parent is PLL1 or PLL0/2 */
82 #define IMX_SC_PM_PARENT_PLL2 3 /* Parent in PLL2 or PLL0/4 */
|
| /Linux-v5.10/arch/arm/boot/dts/ |
| D | stih407-clock.dtsi | 77 compatible = "st,clkgen-pll0";
116 clk_s_c0_pll0: clk-s-c0-pll0 {
118 compatible = "st,clkgen-pll0";
122 clock-output-names = "clk-s-c0-pll0-odf-0";
123 clock-critical = <0>; /* clk-s-c0-pll0-odf-0 */
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| D | stih410-clock.dtsi | 77 compatible = "st,clkgen-pll0";
117 clk_s_c0_pll0: clk-s-c0-pll0 {
119 compatible = "st,clkgen-pll0";
123 clock-output-names = "clk-s-c0-pll0-odf-0";
124 clock-critical = <0>; /* clk-s-c0-pll0-odf-0 */
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| D | stih418-clock.dtsi | 78 compatible = "st,clkgen-pll0";
115 clk_s_c0_pll0: clk-s-c0-pll0 {
117 compatible = "st,clkgen-pll0";
121 clock-output-names = "clk-s-c0-pll0-odf-0";
|
| /Linux-v5.10/arch/arc/boot/dts/ |
| D | abilis_tb10x.dtsi | 48 pll0: oscillator { label
51 clock-output-names = "pll0";
56 clocks = <&pll0>;
62 clocks = <&pll0>;
|
| /Linux-v5.10/drivers/gpu/drm/tegra/ |
| D | hdmi.c | 36 u32 pll0; member
129 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
144 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
162 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
176 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
190 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
208 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
226 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
245 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
264 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
[all …]
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| /Linux-v5.10/drivers/clk/nxp/ |
| D | clk-lpc18xx-cgu.c | 39 /* PLL0 bits common to both audio and USB PLL */
51 /* Register value that gives PLL0 post/pre dividers equal to 1 */
290 * PLL0 uses a special register value encoding. The compute functions below
294 /* Compute PLL0 multiplier from decoded version */
308 /* Compute PLL0 decoded multiplier from binary version */
324 /* Compute PLL0 bandwidth SELI reg from multiplier */
341 /* Compute PLL0 bandwidth SELP reg from multiplier */
|
| /Linux-v5.10/drivers/clk/renesas/ |
| D | r8a7745-cpg-mssr.c | 44 DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN2_PLL0, CLK_MAIN),
190 * MD EXTAL PLL0 PLL1 PLL3
198 * *1 : Table 7.5b indicates VCO output (PLL0 = VCO/3)
205 /* EXTAL div PLL1 mult PLL3 mult PLL0 mult */
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| D | clk-r8a73a4.c | 90 } else if (!strcmp(name, "pll0")) { in r8a73a4_cpg_register_clock()
91 /* PLL0/1 are configurable multiplier clocks. Register them as in r8a73a4_cpg_register_clock()
156 parent_name = "pll0"; in r8a73a4_cpg_register_clock()
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| D | r8a77470-cpg-mssr.c | 44 DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN2_PLL0, CLK_MAIN),
173 * MD EXTAL PLL0 PLL1 PLL3
181 * *1 : Table 7.4 indicates VCO output (PLL0 = VCO)
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| D | r8a7792-cpg-mssr.c | 46 DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN2_PLL0, CLK_MAIN),
164 * MD EXTAL PLL0 PLL1 PLL3
176 * *1 : Table 7.5b indicates VCO output (PLL0 = VCO/3)
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| D | r8a7794-cpg-mssr.c | 48 DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN2_PLL0, CLK_MAIN),
200 * MD EXTAL PLL0 PLL1 PLL3
208 * *1 : Table 7.5c indicates VCO output (PLL0 = VCO/3)
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| D | clk-sh73a0.c | 48 { "zg", "pll0", CPG_FRQCRA, 16 },
130 parent_name = "pll0"; in sh73a0_cpg_register_clock()
|
| /Linux-v5.10/sound/soc/codecs/ |
| D | ak4642.c | 116 #define PLL0 (1 << 4) macro
117 #define PLL_MASK (PLL3 | PLL2 | PLL1 | PLL0)
348 pll = PLL2 | PLL0; in ak4642_dai_set_sysclk()
354 pll = PLL2 | PLL1 | PLL0; in ak4642_dai_set_sysclk()
360 pll = PLL3 | PLL2 | PLL0; in ak4642_dai_set_sysclk()
371 pll = PLL3 | PLL2 | PLL1 | PLL0; in ak4642_dai_set_sysclk()
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| /Linux-v5.10/drivers/clk/ingenic/ |
| D | jz4770-cgu.c | 103 "pll0", CGU_CLK_PLL,
126 /* TODO: PLL1 can depend on PLL0 */
202 /* Those divided clocks can connect to PLL0 or PLL1 */
268 /* Those divided clocks can connect to EXT, PLL0 or PLL1 */
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| /Linux-v5.10/include/dt-bindings/clock/ |
| D | k210-clk.h | 11 * The structure is: in0 -> pll0 -> aclk -> cpu
|
| /Linux-v5.10/Documentation/devicetree/bindings/clock/st/ |
| D | st,clkgen-pll.txt | 12 "st,clkgen-pll0"
|
