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Searched +full:pll +full:- +full:periph (Results 1 – 25 of 35) sorted by relevance

12

/Linux-v5.10/drivers/clk/socfpga/
DMakefile1 # SPDX-License-Identifier: GPL-2.0
2 obj-$(CONFIG_ARCH_SOCFPGA) += clk.o clk-gate.o clk-pll.o clk-periph.o
3 obj-$(CONFIG_ARCH_SOCFPGA) += clk-pll-a10.o clk-periph-a10.o clk-gate-a10.o
4 obj-$(CONFIG_ARCH_STRATIX10) += clk-s10.o
5 obj-$(CONFIG_ARCH_STRATIX10) += clk-pll-s10.o clk-periph-s10.o clk-gate-s10.o
6 obj-$(CONFIG_ARCH_AGILEX) += clk-agilex.o
7 obj-$(CONFIG_ARCH_AGILEX) += clk-pll-s10.o clk-periph-s10.o clk-gate-s10.o
/Linux-v5.10/drivers/clk/tegra/
DMakefile1 # SPDX-License-Identifier: GPL-2.0
2 obj-y += clk.o
3 obj-y += clk-audio-sync.o
4 obj-y += clk-dfll.o
5 obj-y += clk-divider.o
6 obj-y += clk-periph.o
7 obj-y += clk-periph-fixed.o
8 obj-y += clk-periph-gate.o
9 obj-y += clk-pll.o
10 obj-y += clk-pll-out.o
[all …]
Dclk.h1 /* SPDX-License-Identifier: GPL-2.0-only */
9 #include <linux/clk-provider.h>
73 * struct tegra_clk_sync_source - external clock source from codec
75 * @hw: handle between common and hardware-specific interfaces
95 * struct tegra_clk_frac_div - fractional divider clock
97 * @hw: handle between common and hardware-specific interfaces
99 * @flags: hardware-specific flags
106 * TEGRA_DIVIDER_ROUND_UP - This flags indicates to round up the divider value.
107 * TEGRA_DIVIDER_FIXED - Fixed rate PLL dividers has addition override bit, this
108 * flag indicates that this divider is for fixed rate PLL.
[all …]
/Linux-v5.10/drivers/clk/sunxi-ng/
Dccu-sun4i-a10.c1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <linux/clk-provider.h>
26 #include "ccu-sun4i-a10.h"
36 .hw.init = CLK_HW_INIT("pll-core",
44 * The Audio PLL is supposed to have 4 outputs: 3 fixed factors from
46 * pll audio).
48 * With sigma-delta modulation for fractional-N on the audio PLL,
71 .hw.init = CLK_HW_INIT("pll-audio-base",
89 .hw.init = CLK_HW_INIT("pll-video0",
104 .hw.init = CLK_HW_INIT("pll-ve",
[all …]
Dccu-sun8i-a23.c1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/clk-provider.h>
24 #include "ccu-sun8i-a23-a33.h"
38 .hw.init = CLK_HW_INIT("pll-cpux", "osc24M",
45 * The Audio PLL is supposed to have 4 outputs: 3 fixed factors from
47 * pll audio).
49 * With sigma-delta modulation for fractional-N on the audio PLL,
63 static SUNXI_CCU_NM_WITH_SDM_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",
73 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video_clk, "pll-video",
85 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve",
[all …]
Dccu-sun8i-a33.c1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/clk-provider.h>
23 #include "ccu-sun8i-a23-a33.h"
36 .hw.init = CLK_HW_INIT("pll-cpux", "osc24M",
43 * The Audio PLL is supposed to have 4 outputs: 3 fixed factors from
45 * pll audio).
47 * With sigma-delta modulation for fractional-N on the audio PLL,
61 static SUNXI_CCU_NM_WITH_SDM_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",
71 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video_clk, "pll-video",
83 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve",
[all …]
Dccu-sun8i-a83t.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2017 Chen-Yu Tsai. All rights reserved.
6 #include <linux/clk-provider.h>
22 #include "ccu-sun8i-a83t.h"
29 * Neither mainline Linux, U-boot, nor the vendor BSPs use these.
44 .hw.init = CLK_HW_INIT("pll-c0cpux", "osc24M",
58 .hw.init = CLK_HW_INIT("pll-c1cpux", "osc24M",
65 * The Audio PLL has d1, d2 dividers in addition to the usual N, M
66 * factors. Since we only need 2 frequencies from this PLL: 22.5792 MHz
92 .hw.init = CLK_HW_INIT("pll-audio", "osc24M",
[all …]
Dccu-sun5i.c1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/clk-provider.h>
24 #include "ccu-sun5i.h"
34 .hw.init = CLK_HW_INIT("pll-core",
42 * The Audio PLL is supposed to have 4 outputs: 3 fixed factors from
44 * pll audio).
46 * With sigma-delta modulation for fractional-N on the audio PLL,
74 .hw.init = CLK_HW_INIT("pll-audio-base",
91 .hw.init = CLK_HW_INIT("pll-video0",
106 .hw.init = CLK_HW_INIT("pll-ve",
[all …]
Dccu-sun6i-a31.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2016 Chen-Yu Tsai
5 * Chen-Yu Tsai <wens@csie.org>
7 * Based on ccu-sun8i-h3.c by Maxime Ripard.
10 #include <linux/clk-provider.h>
29 #include "ccu-sun6i-a31.h"
31 static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_cpu_clk, "pll-cpu",
41 * The Audio PLL is supposed to have 4 outputs: 3 fixed factors from
43 * pll audio).
45 * With sigma-delta modulation for fractional-N on the audio PLL,
[all …]
Dccu-suniv-f1c100s.c1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/clk-provider.h>
24 #include "ccu-suniv-f1c100s.h"
38 .hw.init = CLK_HW_INIT("pll-cpu", "osc24M",
45 * The Audio PLL is supposed to have 4 outputs: 3 fixed factors from
47 * pll audio).
54 static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",
62 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video_clk, "pll-video",
74 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve",
86 static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_ddr0_clk, "pll-ddr",
[all …]
Dccu-sun8i-a83t.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Copyright 2016 Chen-Yu Tsai
5 * Chen-Yu Tsai <wens@csie.org>
11 #include <dt-bindings/clock/sun8i-a83t-ccu.h>
12 #include <dt-bindings/reset/sun8i-a83t-ccu.h>
21 /* pll-periph is exported to the PRCM block */
26 /* pll-de is exported for the display engine */
Dccu-sun8i-r.c1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/clk-provider.h>
18 #include "ccu-sun8i-r.h"
23 { .fw_name = "pll-periph" },
59 * non-const so we can change it on the A83T.
62 static SUNXI_CCU_GATE_HWS(apb0_pio_clk, "apb0-pio",
64 static SUNXI_CCU_GATE_HWS(apb0_ir_clk, "apb0-ir",
66 static SUNXI_CCU_GATE_HWS(apb0_timer_clk, "apb0-timer",
68 static SUNXI_CCU_GATE_HWS(apb0_rsb_clk, "apb0-rsb",
70 static SUNXI_CCU_GATE_HWS(apb0_uart_clk, "apb0-uart",
[all …]
Dccu-sun9i-a80.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2016 Chen-Yu Tsai. All rights reserved.
6 #include <linux/clk-provider.h>
21 #include "ccu-sun9i-a80.h"
28 * Neither mainline Linux, U-boot, nor the vendor BSPs use these.
43 .hw.init = CLK_HW_INIT("pll-c0cpux", "osc24M",
57 .hw.init = CLK_HW_INIT("pll-c1cpux", "osc24M",
64 * The Audio PLL has d1, d2 dividers in addition to the usual N, M
65 * factors. Since we only need 2 frequencies from this PLL: 22.5792 MHz
79 .hw.init = CLK_HW_INIT("pll-audio", "osc24M",
[all …]
/Linux-v5.10/Documentation/devicetree/bindings/clock/
Dallwinner,sun4i-a10-ccu.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-ccu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
14 "#clock-cells":
17 "#reset-cells":
22 - allwinner,sun4i-a10-ccu
23 - allwinner,sun5i-a10s-ccu
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Daltr_socfpga.txt5 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
8 - compatible : shall be one of the following:
9 "altr,socfpga-pll-clock" - for a PLL clock
10 "altr,socfpga-perip-clock" - The peripheral clock divided from the
11 PLL clock.
12 "altr,socfpga-gate-clk" - Clocks that directly feed peripherals and
15 - reg : shall be the control register offset from CLOCK_MANAGER's base for the clock.
16 - clocks : shall be the input parent clock phandle for the clock. This is
17 either an oscillator or a pll output.
18 - #clock-cells : from common clock binding, shall be set to 0.
[all …]
/Linux-v5.10/arch/mips/bcm63xx/
Dclk.c33 if (clk->set && (clk->usage++) == 0) in clk_enable_unlocked()
34 clk->set(clk, 1); in clk_enable_unlocked()
39 if (clk->set && (--clk->usage) == 0) in clk_disable_unlocked()
40 clk->set(clk, 0); in clk_disable_unlocked()
92 if (clk->id == 0) in enetx_set()
287 * HSSPI PLL
389 return clk->rate; in clk_get_rate()
408 CLKDEV_INIT(NULL, "periph", &clk_periph),
425 CLKDEV_INIT(NULL, "periph", &clk_periph),
428 CLKDEV_INIT("bcm63xx-hsspi.0", "pll", &clk_hsspi_pll),
[all …]
/Linux-v5.10/include/dt-bindings/clock/
Dstratix10-clock.h1 /* SPDX-License-Identifier: GPL-2.0 */
21 /* PLL clocks */
26 /* Periph clocks */
/Linux-v5.10/drivers/clk/nxp/
Dclk-lpc18xx-cgu.c11 #include <linux/clk-provider.h>
18 #include <dt-bindings/clock/lpc18xx-cgu.h>
39 /* PLL0 bits common to both audio and USB PLL */
225 LPC1XX_CGU_BASE_CLK(PERIPH, base_common_src_ids, 0),
268 struct lpc18xx_pll pll; member
303 for (i = LPC18XX_PLL0_MSEL_MAX + 1; x != 0x4000 && i > 0; i--) in lpc18xx_pll0_mdec2msel()
353 struct lpc18xx_pll *pll = to_lpc_pll(hw); in lpc18xx_pll0_recalc_rate() local
356 ctrl = readl(pll->reg + LPC18XX_CGU_PLL0USB_CTRL); in lpc18xx_pll0_recalc_rate()
357 mdiv = readl(pll->reg + LPC18XX_CGU_PLL0USB_MDIV); in lpc18xx_pll0_recalc_rate()
358 npdiv = readl(pll->reg + LPC18XX_CGU_PLL0USB_NP_DIV); in lpc18xx_pll0_recalc_rate()
[all …]
Dclk-lpc32xx.c1 // SPDX-License-Identifier: GPL-2.0-or-later
7 #include <linux/clk-provider.h>
12 #include <dt-bindings/clock/lpc32xx-clock.h>
17 /* Common bitfield definitions for x397 PLL (lock), USB PLL and HCLK PLL */
91 /* System clocks, PLL 397x and HCLK PLL clocks */
215 LPC32XX_CLK_DEFINE(PERIPH, "pclk", CLK_IGNORE_UNUSED,
393 regmap_read(clk_regmap, clk->reg, &val); in clk_mask_enable()
395 if (clk->busy_mask && (val & clk->busy_mask) == clk->busy) in clk_mask_enable()
396 return -EBUSY; in clk_mask_enable()
398 return regmap_update_bits(clk_regmap, clk->reg, in clk_mask_enable()
[all …]
/Linux-v5.10/drivers/clk/imx/
Dclk-imx6sl.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright 2013-2014 Freescale Semiconductor, Inc.
13 #include <dt-bindings/clock/imx6sl-clock.h>
36 static const char *ocram_sels[] = { "periph", "ocram_alt_sels", };
118 * as there is sleep function in PLL wait function), so here we just slow
122 * 396MHz -> 132MHz;
123 * 792MHz -> 158.4MHz;
124 * 996MHz -> 142.3MHz;
200 clk_hw_data->num = IMX6SL_CLK_END; in imx6sl_clocks_init()
201 hws = clk_hw_data->hws; in imx6sl_clocks_init()
[all …]
Dclk-imx6q.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 2011-2013 Freescale Semiconductor, Inc.
12 #include <linux/clk-provider.h>
19 #include <dt-bindings/clock/imx6qdl-clock.h>
30 static const char *axi_sels[] = { "periph", "pll2_pfd2_396m", "periph", "pll3_pfd1_540m", };
156 return -ENOENT; in ldb_di_sel_by_clock_id()
167 return -ENOENT; in ldb_di_sel_by_clock_id()
179 num_parents = of_count_phandle_with_args(node, "assigned-clock-parents", in of_assigned_ldb_sels()
180 "#clock-cells"); in of_assigned_ldb_sels()
182 rc = of_parse_phandle_with_args(node, "assigned-clock-parents", in of_assigned_ldb_sels()
[all …]
/Linux-v5.10/drivers/clk/samsung/
Dclk-exynos5250.c1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <dt-bindings/clock/exynos5250.h>
11 #include <linux/clk-provider.h>
17 #include "clk-cpu.h"
18 #include "clk-exynos5-subcmu.h"
733 [apll] = PLL(pll_35xx, CLK_FOUT_APLL, "fout_apll", "fin_pll", APLL_LOCK,
735 [mpll] = PLL(pll_35xx, CLK_FOUT_MPLL, "fout_mpll", "fin_pll", MPLL_LOCK,
737 [bpll] = PLL(pll_35xx, CLK_FOUT_BPLL, "fout_bpll", "fin_pll", BPLL_LOCK,
739 [gpll] = PLL(pll_35xx, CLK_FOUT_GPLL, "fout_gpll", "fin_pll", GPLL_LOCK,
741 [cpll] = PLL(pll_35xx, CLK_FOUT_CPLL, "fout_cpll", "fin_pll", CPLL_LOCK,
[all …]
Dclk-exynos4.c1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <dt-bindings/clock/exynos4.h>
13 #include <linux/clk-provider.h>
19 #include "clk-cpu.h"
295 /* Exynos 4210-specific parent groups */
334 /* Exynos 4x12-specific parent groups */
874 GATE(CLK_I2C_HDMI, "i2c-hdmi", "aclk100", GATE_IP_PERIL, 14,
1022 np = of_find_compatible_node(NULL, NULL, "samsung,exynos4210-chipid"); in exynos4_get_xom()
1064 { .compatible = "samsung,clock-xxti", .data = (void *)0, },
1065 { .compatible = "samsung,clock-xusbxti", .data = (void *)1, },
[all …]
/Linux-v5.10/drivers/clk/qcom/
Dgpucc-msm8998.c1 // SPDX-License-Identifier: GPL-2.0
13 #include <linux/clk-provider.h>
15 #include <linux/reset-controller.h>
17 #include <dt-bindings/clock/qcom,gpucc-msm8998.h>
20 #include "clk-regmap.h"
21 #include "clk-regmap-divider.h"
22 #include "clk-alpha-pll.h"
23 #include "clk-rcg.h"
24 #include "clk-branch.h"
309 { .compatible = "qcom,msm8998-gpucc" },
[all …]
/Linux-v5.10/arch/arm64/boot/dts/allwinner/
Dsun50i-a100.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ or MIT)
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/sun50i-a100-ccu.h>
8 #include <dt-bindings/clock/sun50i-a100-r-ccu.h>
9 #include <dt-bindings/reset/sun50i-a100-ccu.h>
10 #include <dt-bindings/reset/sun50i-a100-r-ccu.h>
13 interrupt-parent = <&gic>;
14 #address-cells = <2>;
15 #size-cells = <2>;
18 #address-cells = <1>;
[all …]

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