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/Linux-v5.10/drivers/clk/mediatek/
Dclk-pll.c1 // SPDX-License-Identifier: GPL-2.0-only
14 #include "clk-mtk.h"
21 #define CON0_ISO_EN BIT(1)
33 * a divider in the PLL feedback loop which consists of 7 bits for the integer
35 * have a 3 bit power-of-two post divider.
57 struct mtk_clk_pll *pll = to_mtk_clk_pll(hw); in mtk_pll_is_prepared() local
59 return (readl(pll->base_addr + REG_CON0) & CON0_BASE_EN) != 0; in mtk_pll_is_prepared()
62 static unsigned long __mtk_pll_recalc_rate(struct mtk_clk_pll *pll, u32 fin, in __mtk_pll_recalc_rate() argument
65 int pcwbits = pll->data->pcwbits; in __mtk_pll_recalc_rate()
71 /* The fractional part of the PLL divider. */ in __mtk_pll_recalc_rate()
[all …]
/Linux-v5.10/drivers/clk/tegra/
Dclk-pll.c1 // SPDX-License-Identifier: GPL-2.0-only
11 #include <linux/clk-provider.h>
31 #define PLL_MISC_CPCON_MASK ((1 << PLL_MISC_CPCON_WIDTH) - 1)
34 #define PLL_MISC_LFCON_MASK ((1 << PLL_MISC_LFCON_WIDTH) - 1)
37 #define PLL_MISC_VCOCON_MASK ((1 << PLL_MISC_VCOCON_WIDTH) - 1)
159 #define PLLSS_EN_DITHER 1
196 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERUP BIT(1)
207 #define UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE BIT(1)
230 #define pll_readl(offset, p) readl_relaxed(p->clk_base + offset)
231 #define pll_readl_base(p) pll_readl(p->params->base_reg, p)
[all …]
/Linux-v5.10/drivers/clk/baikal-t1/
Dccu-pll.c1 // SPDX-License-Identifier: GPL-2.0-only
9 * Baikal-T1 CCU PLL interface driver
12 #define pr_fmt(fmt) "bt1-ccu-pll: " fmt
20 #include <linux/clk-provider.h>
29 #include "ccu-pll.h"
33 #define CCU_PLL_CTL_RST BIT(1)
49 ((CCU_PLL_CTL_CLKR_MASK >> CCU_PLL_CTL_CLKR_FLD) + 1)
51 ((CCU_PLL_CTL_CLKF_MASK >> (CCU_PLL_CTL_CLKF_FLD + 1)) + 1)
53 ((CCU_PLL_CTL_CLKOD_MASK >> CCU_PLL_CTL_CLKOD_FLD) + 1)
55 ((CCU_PLL_CTL1_BWADJ_MASK >> CCU_PLL_CTL1_BWADJ_FLD) + 1)
[all …]
/Linux-v5.10/drivers/video/fbdev/aty/
Dmach64_ct.c1 // SPDX-License-Identifier: GPL-2.0
18 static int aty_valid_pll_ct (const struct fb_info *info, u32 vclk_per, struct pll_ct *pll);
19 static int aty_dsp_gt (const struct fb_info *info, u32 bpp, struct pll_ct *pll);
20 static int aty_var_to_pll_ct(const struct fb_info *info, u32 vclk_per, u32 bpp, union aty_pll *pll);
21 static u32 aty_pll_to_var_ct(const struct fb_info *info, const union aty_pll *pll);
53 * CLK = ----------------------
64 * are 1,2,4,8 and for some clocks other values are available too.
70 * XCLK The clock rate of the on-chip memory
77 * SCLK Multi-purpose clock
79 * - MCLK and XCLK use the same FB_DIV
[all …]
/Linux-v5.10/arch/mips/ath79/
Dclock.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
17 #include <linux/clk-provider.h>
20 #include <dt-bindings/clock/ath79-clk.h>
24 #include <asm/mach-ath79/ath79.h>
25 #include <asm/mach-ath79/ar71xx_regs.h>
99 u32 pll; in ar71xx_clocks_init() local
105 pll = __raw_readl(pll_base + AR71XX_PLL_REG_CPU_CONFIG); in ar71xx_clocks_init()
107 div = ((pll >> AR71XX_PLL_FB_SHIFT) & AR71XX_PLL_FB_MASK) + 1; in ar71xx_clocks_init()
110 div = ((pll >> AR71XX_CPU_DIV_SHIFT) & AR71XX_CPU_DIV_MASK) + 1; in ar71xx_clocks_init()
[all …]
/Linux-v5.10/drivers/media/i2c/
Dsmiapp-pll.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * drivers/media/i2c/smiapp-pll.c
7 * Copyright (C) 2011--2012 Nokia Corporation
16 #include "smiapp-pll.h"
21 return max_t(uint32_t, 1, a & ~1); in clk_div_even()
27 if (a == 1) in clk_div_even_up()
28 return 1; in clk_div_even_up()
29 return (a + 1) & ~1; in clk_div_even_up()
34 if (a == 1) in is_one_or_even()
35 return 1; in is_one_or_even()
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/Linux-v5.10/drivers/clk/rockchip/
Dclk-pll.c1 // SPDX-License-Identifier: GPL-2.0-or-later
7 * Author: Xing Zheng <zhengxing@rock-chips.com>
14 #include <linux/clk-provider.h>
51 struct rockchip_clk_pll *pll, unsigned long rate) in rockchip_get_pll_settings() argument
53 const struct rockchip_pll_rate_table *rate_table = pll->rate_table; in rockchip_get_pll_settings()
56 for (i = 0; i < pll->rate_count; i++) { in rockchip_get_pll_settings()
67 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); in rockchip_pll_round_rate() local
68 const struct rockchip_pll_rate_table *rate_table = pll->rate_table; in rockchip_pll_round_rate()
72 for (i = 0; i < pll->rate_count; i++) { in rockchip_pll_round_rate()
78 return rate_table[i - 1].rate; in rockchip_pll_round_rate()
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/Linux-v5.10/drivers/clk/meson/
Dclk-pll.c1 // SPDX-License-Identifier: GPL-2.0
11 * In the most basic form, a Meson PLL is composed as follows:
13 * PLL
14 * +--------------------------------+
16 * | +--+ |
17 * in >>-----[ /N ]--->| | +-----+ |
18 * | | |------| DCO |---->> out
19 * | +--------->| | +--v--+ |
20 * | | +--+ | |
22 * | +--[ *(M + (F/Fmax) ]<--+ |
[all …]
/Linux-v5.10/drivers/clk/qcom/
Dclk-alpha-pll.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/clk-provider.h>
12 #include "clk-alpha-pll.h"
15 #define PLL_MODE(p) ((p)->offset + 0x0)
17 # define PLL_BYPASSNL BIT(1)
34 #define PLL_L_VAL(p) ((p)->offset + (p)->regs[PLL_OFF_L_VAL])
35 #define PLL_CAL_L_VAL(p) ((p)->offset + (p)->regs[PLL_OFF_CAL_L_VAL])
36 #define PLL_ALPHA_VAL(p) ((p)->offset + (p)->regs[PLL_OFF_ALPHA_VAL])
37 #define PLL_ALPHA_VAL_U(p) ((p)->offset + (p)->regs[PLL_OFF_ALPHA_VAL_U])
39 #define PLL_USER_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_USER_CTL])
[all …]
Dclk-pll.c1 // SPDX-License-Identifier: GPL-2.0-only
12 #include <linux/clk-provider.h>
17 #include "clk-pll.h"
21 #define PLL_BYPASSNL BIT(1)
26 struct clk_pll *pll = to_clk_pll(hw); in clk_pll_enable() local
31 ret = regmap_read(pll->clkr.regmap, pll->mode_reg, &val); in clk_pll_enable()
39 /* Disable PLL bypass mode. */ in clk_pll_enable()
40 ret = regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_BYPASSNL, in clk_pll_enable()
47 * de-asserting the reset. Delay 10us just to be safe. in clk_pll_enable()
51 /* De-assert active-low PLL reset. */ in clk_pll_enable()
[all …]
/Linux-v5.10/drivers/clk/sprd/
Dpll.c1 // SPDX-License-Identifier: GPL-2.0
3 // Spreadtrum pll clock driver
13 #include "pll.h"
18 #define pindex(pll, member) \ argument
19 (pll->factors[member].shift / (8 * sizeof(pll->regs_num)))
21 #define pshift(pll, member) \ argument
22 (pll->factors[member].shift % (8 * sizeof(pll->regs_num)))
24 #define pwidth(pll, member) \ argument
25 pll->factors[member].width
27 #define pmask(pll, member) \ argument
[all …]
/Linux-v5.10/drivers/clk/bcm/
Dclk-iproc-pll.c16 #include <linux/clk-provider.h>
23 #include "clk-iproc.h"
29 * PLL MACRO_SELECT modes 0 to 5 choose pre-calculated PLL output frequencies
30 * from a look-up table. Mode 7 allows user to manipulate PLL clock dividers
34 /* number of delay loops waiting for PLL to lock */
85 struct iproc_pll *pll; member
100 return -EINVAL; in pll_calc_param()
102 residual = target_rate - (ndiv_int * parent_rate); in pll_calc_param()
112 vco_out->ndiv_int = ndiv_int; in pll_calc_param()
113 vco_out->ndiv_frac = ndiv_frac; in pll_calc_param()
[all …]
Dclk-iproc-armpll.c17 #include <linux/clk-provider.h>
23 #include "clk-iproc.h"
76 static unsigned int __get_fid(struct iproc_arm_pll *pll) in __get_fid() argument
81 val = readl(pll->base + IPROC_CLK_ARM_DIV_OFFSET); in __get_fid()
82 if (val & (1 << IPROC_CLK_ARM_DIV_PLL_SELECT_OVERRIDE_SHIFT)) in __get_fid()
90 val = readl(pll->base + IPROC_CLK_POLICY_FREQ_OFFSET); in __get_fid()
94 val = readl(pll->base + IPROC_CLK_POLICY_DBG_OFFSET); in __get_fid()
98 pr_debug("%s: fid override %u->%u\n", __func__, fid, in __get_fid()
111 * - 25 MHz Crystal
112 * - System clock
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/Linux-v5.10/drivers/gpu/drm/msm/dsi/pll/
Ddsi_pll_14nm.c1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/clk-provider.h>
13 * DSI PLL 14nm - clock diagram (eg: DSI0):
18 * +----+ | +----+
19 * dsi0vco_clk ---| n1 |--o--| /8 |-- dsi0pllbyte
20 * +----+ | +----+
22 * | +----+ |
23 * o---| /2 |--o--|\
24 * | +----+ | \ +----+
25 * | | |--| n2 |-- dsi0pll
[all …]
Ddsi_pll_7nm.c2 * SPDX-License-Identifier: GPL-2.0
7 #include <linux/clk-provider.h>
14 * DSI PLL 7nm - clock diagram (eg: DSI0): TODO: updated CPHY diagram
19 * +---------+ | +----------+ | +----+
20 * dsi0vco_clk ---| out_div |--o--| divl_3_0 |--o--| /8 |-- dsi0_phy_pll_out_byteclk
21 * +---------+ | +----------+ | +----+
25 * | | +----+ | |\ dsi0_pclk_mux
26 * | |--| /2 |--o--| \ |
27 * | | +----+ | \ | +---------+
28 …* | --------------| |--o--| div_7_4 |-- dsi0_phy_pll_…
[all …]
/Linux-v5.10/drivers/clk/imx/
Dclk-pll14xx.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright 2017-2018 NXP.
7 #include <linux/clk-provider.h>
48 PLL_1416X_RATE(1500000000U, 375, 3, 1),
49 PLL_1416X_RATE(1400000000U, 350, 3, 1),
50 PLL_1416X_RATE(1200000000U, 300, 3, 1),
51 PLL_1416X_RATE(1000000000U, 250, 3, 1),
52 PLL_1416X_RATE(800000000U, 200, 3, 1),
59 PLL_1443X_RATE(1039500000U, 173, 2, 1, 16384),
90 struct clk_pll14xx *pll, unsigned long rate) in imx_get_pll_settings() argument
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Dclk-pllv3.c1 // SPDX-License-Identifier: GPL-2.0-or-later
7 #include <linux/clk-provider.h>
32 * struct clk_pllv3 - IMX PLL clock version 3
34 * @base: base address of PLL registers
35 * @power_bit: pll power bit mask
36 * @powerup_set: set power_bit to power up the PLL
43 * IMX PLL clock version 3, found on i.MX6 series. Divider for pllv3
60 static int clk_pllv3_wait_lock(struct clk_pllv3 *pll) in clk_pllv3_wait_lock() argument
62 u32 val = readl_relaxed(pll->base) & pll->power_bit; in clk_pllv3_wait_lock()
64 /* No need to wait for lock when pll is not powered up */ in clk_pllv3_wait_lock()
[all …]
Dclk-pllv1.c1 // SPDX-License-Identifier: GPL-2.0
3 #include <linux/clk-provider.h>
12 * pll v1
16 * @base base address of pll registers
18 * PLL clock version 1, found on i.MX1/21/25/27/31/35
22 #define MFN_SIGN (BIT(MFN_BITS - 1))
23 #define MFN_MASK (MFN_SIGN - 1)
33 static inline bool is_imx1_pllv1(struct clk_pllv1 *pll) in is_imx1_pllv1() argument
35 return pll->type == IMX_PLLV1_IMX1; in is_imx1_pllv1()
38 static inline bool is_imx21_pllv1(struct clk_pllv1 *pll) in is_imx21_pllv1() argument
[all …]
Dclk-sscg-pll.c1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 * Documentation for this SCCG pll can be found at:
8 * https://www.nxp.com/docs/en/reference-manual/IMX8MDQLQRM.pdf#page=834
11 #include <linux/clk-provider.h>
21 /* PLL CFGs */
30 #define PLL_DIVQ_MASK GENMASK(6, 1)
36 /* These are the specification limits for the SSCG PLL */
98 static int clk_sscg_pll_wait_lock(struct clk_sscg_pll *pll) in clk_sscg_pll_wait_lock() argument
102 val = readl_relaxed(pll->base + PLL_CFG0); in clk_sscg_pll_wait_lock()
106 return readl_poll_timeout(pll->base, val, val & PLL_LOCK_MASK, in clk_sscg_pll_wait_lock()
[all …]
/Linux-v5.10/drivers/gpu/drm/msm/hdmi/
Dhdmi_phy_8996.c1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/clk-provider.h>
33 /* pll mmio base */
81 static inline struct hdmi_phy *pll_get_phy(struct hdmi_pll_8996 *pll) in pll_get_phy() argument
83 return platform_get_drvdata(pll->pdev); in pll_get_phy()
86 static inline void hdmi_pll_write(struct hdmi_pll_8996 *pll, int offset, in hdmi_pll_write() argument
89 msm_writel(data, pll->mmio_qserdes_com + offset); in hdmi_pll_write()
92 static inline u32 hdmi_pll_read(struct hdmi_pll_8996 *pll, int offset) in hdmi_pll_read() argument
94 return msm_readl(pll->mmio_qserdes_com + offset); in hdmi_pll_read()
97 static inline void hdmi_tx_chan_write(struct hdmi_pll_8996 *pll, int channel, in hdmi_tx_chan_write() argument
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/Linux-v5.10/drivers/video/fbdev/omap2/omapfb/dss/
Dvideo-pll.c1 // SPDX-License-Identifier: GPL-2.0-only
20 struct dss_pll pll; member
32 REG_MOD(vpll->clkctrl_base, 1, 14, 14); /* CIO_CLK_ICG */ in dss_dpll_enable_scp_clk()
37 REG_MOD(vpll->clkctrl_base, 0, 14, 14); /* CIO_CLK_ICG */ in dss_dpll_disable_scp_clk()
42 REG_MOD(vpll->clkctrl_base, 2, 31, 30); /* PLL_POWER_ON_ALL */ in dss_dpll_power_enable()
45 * DRA7x PLL CTRL's PLL_PWR_STATUS seems to always return 0, in dss_dpll_power_enable()
48 msleep(1); in dss_dpll_power_enable()
53 REG_MOD(vpll->clkctrl_base, 0, 31, 30); /* PLL_POWER_OFF */ in dss_dpll_power_disable()
56 static int dss_video_pll_enable(struct dss_pll *pll) in dss_video_pll_enable() argument
58 struct dss_video_pll *vpll = container_of(pll, struct dss_video_pll, pll); in dss_video_pll_enable()
[all …]
/Linux-v5.10/drivers/gpu/drm/omapdrm/dss/
Dvideo-pll.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
18 struct dss_pll pll; member
30 REG_MOD(vpll->clkctrl_base, 1, 14, 14); /* CIO_CLK_ICG */ in dss_dpll_enable_scp_clk()
35 REG_MOD(vpll->clkctrl_base, 0, 14, 14); /* CIO_CLK_ICG */ in dss_dpll_disable_scp_clk()
40 REG_MOD(vpll->clkctrl_base, 2, 31, 30); /* PLL_POWER_ON_ALL */ in dss_dpll_power_enable()
43 * DRA7x PLL CTRL's PLL_PWR_STATUS seems to always return 0, in dss_dpll_power_enable()
46 msleep(1); in dss_dpll_power_enable()
51 REG_MOD(vpll->clkctrl_base, 0, 31, 30); /* PLL_POWER_OFF */ in dss_dpll_power_disable()
54 static int dss_video_pll_enable(struct dss_pll *pll) in dss_video_pll_enable() argument
[all …]
/Linux-v5.10/drivers/clk/mxs/
Dclk-pll.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 #include <linux/clk-provider.h>
14 * struct clk_pll - mxs pll clock
15 * @hw: clk_hw for the pll
16 * @base: base address of the pll
18 * @rate: the clock rate of the pll
20 * The mxs pll is a fixed rate clock with power and gate control,
34 struct clk_pll *pll = to_clk_pll(hw); in clk_pll_prepare() local
36 writel_relaxed(1 << pll->power, pll->base + SET); in clk_pll_prepare()
45 struct clk_pll *pll = to_clk_pll(hw); in clk_pll_unprepare() local
[all …]
/Linux-v5.10/drivers/clk/x86/
Dclk-cgu-pll.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/clk-provider.h>
14 #include "clk-cgu.h"
41 struct lgm_clk_pll *pll = to_lgm_clk_pll(hw); in lgm_pll_recalc_rate() local
45 spin_lock_irqsave(&pll->lock, flags); in lgm_pll_recalc_rate()
46 mult = lgm_get_clk_val(pll->membase, PLL_REF_DIV(pll->reg), 0, 12); in lgm_pll_recalc_rate()
47 div = lgm_get_clk_val(pll->membase, PLL_REF_DIV(pll->reg), 18, 6); in lgm_pll_recalc_rate()
48 frac = lgm_get_clk_val(pll->membase, pll->reg, 2, 24); in lgm_pll_recalc_rate()
49 spin_unlock_irqrestore(&pll->lock, flags); in lgm_pll_recalc_rate()
51 if (pll->type == TYPE_LJPLL) in lgm_pll_recalc_rate()
[all …]
/Linux-v5.10/drivers/clk/st/
Dclkgen-pll.c1 // SPDX-License-Identifier: GPL-2.0-or-later
15 #include <linux/clk-provider.h>
24 * PLL configuration register bits for PLL3200 C32
35 * PLL configuration register bits for PLL4600 C28
71 .num_odfs = 1,
84 .num_odfs = 1,
97 .num_odfs = 1,
101 .cp = CLKGEN_FIELD(0x1a8, C32_CP_MASK, 1),
102 .switch2pll = CLKGEN_FIELD(0x1a4, 0x1, 1),
114 .num_odfs = 1,
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