/Linux-v5.4/drivers/media/cec/ |
D | cec-pin.c | 10 #include <media/cec-pin.h> 11 #include "cec-pin-priv.h" 111 static void cec_pin_update(struct cec_pin *pin, bool v, bool force) in cec_pin_update() argument 113 if (!force && v == pin->adap->cec_pin_is_high) in cec_pin_update() 116 pin->adap->cec_pin_is_high = v; in cec_pin_update() 117 if (atomic_read(&pin->work_pin_num_events) < CEC_NUM_PIN_EVENTS) { in cec_pin_update() 120 if (pin->work_pin_events_dropped) { in cec_pin_update() 121 pin->work_pin_events_dropped = false; in cec_pin_update() 124 pin->work_pin_events[pin->work_pin_events_wr] = ev; in cec_pin_update() 125 pin->work_pin_ts[pin->work_pin_events_wr] = ktime_get(); in cec_pin_update() [all …]
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/Linux-v5.4/Documentation/devicetree/bindings/pinctrl/ |
D | pinctrl-mt7622.txt | 10 - #gpio-cells: Should be two. The first cell is the pin number and the 23 phrase "pin configuration node". 25 MT7622 pin configuration nodes act as a container for an arbitrary number of 27 pin, a group, or a list of pins or groups. This configuration can include the 28 mux function to select on those pin(s)/group(s), and various pin configuration 55 - pins: An array of strings. Each string contains the name of a pin. 83 pins can be referenced via the pin names as the below table shown and the 88 Pin #: Valid values for pins 90 PIN 0: "GPIO_A" 91 PIN 1: "I2S1_IN" [all …]
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D | pinctrl-bindings.txt | 3 Hardware modules that control pin multiplexing or configuration parameters 4 such as pull-up/down, tri-state, drive-strength etc are designated as pin 5 controllers. Each pin controller must be represented as a node in device tree, 8 Hardware modules whose signals are affected by pin configuration are 12 For a client device to operate correctly, certain pin controllers must 13 set up certain specific pin configurations. Some client devices need a 14 single static pin configuration, e.g. set up during initialization. Others 21 for client device device tree nodes to map those state names to the pin 24 Note that pin controllers themselves may also be client devices of themselves. 25 For example, a pin controller may set up its own "active" state when the [all …]
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D | samsung-pinctrl.txt | 1 Samsung GPIO and Pin Mux/Config controller 3 Samsung's ARM based SoC's integrates a GPIO and Pin mux/config hardware 10 - "samsung,s3c2412-pinctrl": for S3C2412-compatible pin-controller, 11 - "samsung,s3c2416-pinctrl": for S3C2416-compatible pin-controller, 12 - "samsung,s3c2440-pinctrl": for S3C2440-compatible pin-controller, 13 - "samsung,s3c2450-pinctrl": for S3C2450-compatible pin-controller, 14 - "samsung,s3c64xx-pinctrl": for S3C64xx-compatible pin-controller, 15 - "samsung,s5pv210-pinctrl": for S5PV210-compatible pin-controller, 16 - "samsung,exynos3250-pinctrl": for Exynos3250 compatible pin-controller. 17 - "samsung,exynos4210-pinctrl": for Exynos4210 compatible pin-controller. [all …]
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D | renesas,pfc-pinctrl.txt | 1 * Renesas Pin Function Controller (GPIO and Pin Mux/Config) 3 The Pin Function Controller (PFC) is a Pin Mux/Config controller. On SH73A0, 7 Pin Control 13 - "renesas,pfc-emev2": for EMEV2 (EMMA Mobile EV2) compatible pin-controller. 14 - "renesas,pfc-r8a73a4": for R8A73A4 (R-Mobile APE6) compatible pin-controller. 15 - "renesas,pfc-r8a7740": for R8A7740 (R-Mobile A1) compatible pin-controller. 16 - "renesas,pfc-r8a7743": for R8A7743 (RZ/G1M) compatible pin-controller. 17 - "renesas,pfc-r8a7744": for R8A7744 (RZ/G1N) compatible pin-controller. 18 - "renesas,pfc-r8a7745": for R8A7745 (RZ/G1E) compatible pin-controller. 19 - "renesas,pfc-r8a77470": for R8A77470 (RZ/G1C) compatible pin-controller. [all …]
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D | renesas,rza1-pinctrl.txt | 1 Renesas RZ/A1 combined Pin and GPIO controller 3 The Renesas SoCs of the RZ/A1 family feature a combined Pin and GPIO controller, 5 Pin multiplexing and GPIO configuration is performed on a per-pin basis 9 Up to 8 different alternate function modes exist for each single pin. 11 Pin controller node 21 address base and length of the memory area where the pin controller 25 Pin controller node for RZ/A1H SoC (r7s72100) 27 pinctrl: pin-controller@fcfe3000 { 36 The child nodes of the pin controller node describe a pin multiplexing 39 - Pin multiplexing sub-nodes: [all …]
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/Linux-v5.4/arch/arm/boot/dts/ |
D | sama5d3_lcd.dtsi | 60 <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD0 pin */ 61 AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD1 pin */ 62 AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD2 pin */ 63 AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD3 pin */ 64 AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD4 pin */ 65 AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD5 pin */ 66 AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD6 pin */ 67 AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD7 pin */ 68 AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD8 pin */ 69 AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD9 pin */ [all …]
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D | s5pv210-pinctrl.dtsi | 274 samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 275 samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; 276 samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 281 samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 282 samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; 283 samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 288 samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 289 samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; 290 samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 295 samsung,pin-function = <EXYNOS_PIN_FUNC_2>; [all …]
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D | exynos4210-pinctrl.dtsi | 3 * Samsung's Exynos4210 SoC pin-mux and pin-config device tree source 10 * Samsung's Exynos4210 SoC pin-mux and pin-config optiosn are listed as device 147 samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 148 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 149 samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 154 samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 155 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 156 samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 161 samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 162 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; [all …]
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D | exynos5420-pinctrl.dtsi | 3 * Samsung's Exynos5420 SoC pin-mux and pin-config device tree source 8 * Samsung's Exynos5420 SoC pin-mux and pin-config options are listed as device 63 samsung,pin-function = <EXYNOS_PIN_FUNC_3>; 64 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 65 samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; 70 samsung,pin-function = <EXYNOS_PIN_FUNC_3>; 71 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 72 samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; 162 samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 163 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; [all …]
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D | exynos4412-pinctrl.dtsi | 3 * Samsung's Exynos4412 SoCs pin-mux and pin-config device tree source 8 * Samsung's Exynos4412 SoCs pin-mux and pin-config optiosn are listed as device 17 samsung,pin-con-pdn = <EXYNOS_PIN_PDN_ ##_mode>; \ 18 samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_ ##_pull>; \ 128 samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 129 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 130 samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 135 samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 136 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 137 samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; [all …]
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D | s3c64xx-pinctrl.dtsi | 4 * - pin control-related definitions 8 * Samsung's S3C64xx SoCs pin banks, pin-mux and pin-config options are 16 * Pin banks 131 * Pin groups 136 samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 137 samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; 142 samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 143 samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; 148 samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 149 samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; [all …]
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D | exynos3250-pinctrl.dtsi | 3 * Samsung's Exynos3250 SoCs pin-mux and pin-config device tree source 8 * Samsung's Exynos3250 SoCs pin-mux and pin-config optiosn are listed as device 17 samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>; \ 18 samsung,pin-pud = <EXYNOS_PIN_PULL_ ##_pull>; \ 19 samsung,pin-drv = <EXYNOS4_PIN_DRV_ ##_drv>; \ 25 samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; \ 26 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; \ 27 samsung,pin-drv = <EXYNOS4_PIN_DRV_ ##_drv>; \ 33 samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; \ 34 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; \ [all …]
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D | at91sam9x5_lcd.dtsi | 63 <AT91_PIOC 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD0 pin */ 64 AT91_PIOC 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD1 pin */ 65 AT91_PIOC 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD2 pin */ 66 AT91_PIOC 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD3 pin */ 67 AT91_PIOC 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD4 pin */ 68 AT91_PIOC 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD5 pin */ 69 AT91_PIOC 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD6 pin */ 70 AT91_PIOC 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD7 pin */ 71 AT91_PIOC 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD8 pin */ 72 AT91_PIOC 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD9 pin */ [all …]
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D | exynos5250-pinctrl.dtsi | 3 * Samsung's Exynos5250 SoC pin-mux and pin-config device tree source 8 * Samsung's Exynos5250 SoC pin-mux and pin-config optiosn are listed as device 202 samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 203 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 204 samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 209 samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 210 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 211 samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 216 samsung,pin-function = <EXYNOS_PIN_FUNC_3>; 217 samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; [all …]
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D | exynos5260-pinctrl.dtsi | 3 * Samsung's Exynos5260 SoC pin-mux and pin-config device tree source 8 * Samsung's Exynos5260 SoC pin-mux and pin-config options are listed as device 201 samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 202 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 203 samsung,pin-drv = <EXYNOS5260_PIN_DRV_LV1>; 208 samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 209 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 210 samsung,pin-drv = <EXYNOS5260_PIN_DRV_LV1>; 215 samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 216 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; [all …]
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D | exynos5410-pinctrl.dtsi | 3 * Exynos5410 SoC pin-mux and pin-config device tree source 282 samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 283 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 284 samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; 289 samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 290 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 291 samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; 296 samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 297 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 298 samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; [all …]
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/Linux-v5.4/arch/mips/include/asm/mach-pnx833x/ |
D | gpio.h | 42 /* Select GPIO direction for a pin */ 43 static inline void pnx833x_gpio_select_input(unsigned int pin) in pnx833x_gpio_select_input() argument 45 if (pin < 32) in pnx833x_gpio_select_input() 46 CLEAR_REG_BIT(PNX833X_PIO_DIR, pin); in pnx833x_gpio_select_input() 48 CLEAR_REG_BIT(PNX833X_PIO_DIR2, pin & 31); in pnx833x_gpio_select_input() 50 static inline void pnx833x_gpio_select_output(unsigned int pin) in pnx833x_gpio_select_output() argument 52 if (pin < 32) in pnx833x_gpio_select_output() 53 SET_REG_BIT(PNX833X_PIO_DIR, pin); in pnx833x_gpio_select_output() 55 SET_REG_BIT(PNX833X_PIO_DIR2, pin & 31); in pnx833x_gpio_select_output() 58 /* Select GPIO or alternate function for a pin */ [all …]
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/Linux-v5.4/arch/arm64/boot/dts/exynos/ |
D | exynos5433-pinctrl.dtsi | 3 * Samsung's Exynos5433 SoC pin-mux and pin-config device tree source 8 * Samsung's Exynos5433 SoC pin-mux and pin-config options are listed as device 14 #define PIN(_func, _pin, _pull, _drv) \ macro 17 samsung,pin-function = <EXYNOS_PIN_FUNC_ ##_func>; \ 18 samsung,pin-pud = <EXYNOS_PIN_PULL_ ##_pull>; \ 19 samsung,pin-drv = <EXYNOS5433_PIN_DRV_ ##_drv>; \ 134 samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 135 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 136 samsung,pin-drv = <EXYNOS5433_PIN_DRV_FAST_SR1>; 141 samsung,pin-function = <EXYNOS_PIN_FUNC_3>; [all …]
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D | exynos7-pinctrl.dtsi | 3 * Samsung's Exynos7 SoC pin-mux and pin-config device tree source 8 * Samsung's Exynos7 SoC pin-mux and pin-config options are listed as 189 samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 190 samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; 191 samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 196 samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 197 samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; 198 samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 203 samsung,pin-function = <EXYNOS_PIN_FUNC_3>; 204 samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; [all …]
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/Linux-v5.4/drivers/pinctrl/qcom/ |
D | pinctrl-ssbi-mpp.c | 88 * struct pm8xxx_pin_data - dynamic configuration for a pin 91 * @mode: operating mode for the pin (digital, analog or current sink) 92 * @input: pin is input 93 * @output: pin is output 94 * @high_z: pin is floating 165 struct pm8xxx_pin_data *pin) in pm8xxx_mpp_update() argument 173 switch (pin->mode) { in pm8xxx_mpp_update() 175 if (pin->dtest) { in pm8xxx_mpp_update() 177 ctrl = pin->dtest - 1; in pm8xxx_mpp_update() 178 } else if (pin->input && pin->output) { in pm8xxx_mpp_update() [all …]
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D | pinctrl-ssbi-gpio.c | 57 * struct pm8xxx_pin_data - dynamic configuration for a pin 62 * @mode: operating mode for the pin (input/output) 69 * @disable: pin disabled / configured as tristate 71 * @inverted: pin logic is inverted 131 struct pm8xxx_pin_data *pin, int bank) in pm8xxx_read_bank() argument 136 ret = regmap_write(pctrl->regmap, pin->reg, val); in pm8xxx_read_bank() 142 ret = regmap_read(pctrl->regmap, pin->reg, &val); in pm8xxx_read_bank() 152 struct pm8xxx_pin_data *pin, in pm8xxx_write_bank() argument 161 ret = regmap_write(pctrl->regmap, pin->reg, val); in pm8xxx_write_bank() 231 struct pm8xxx_pin_data *pin = pctrl->desc.pins[group].drv_data; in pm8xxx_pinmux_set_mux() local [all …]
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/Linux-v5.4/drivers/pinctrl/ |
D | pinctrl-rza1.c | 3 * Combined GPIO and pin controller support for Renesas RZ/A1 (r7s72100) SoC 9 * This pin controller/gpio combined driver supports Renesas devices of RZ/A1 56 * Use 16 lower bits [15:0] for pin identifier 57 * Use 16 higher bits [31:16] for pin mux function 69 /* Pin mux flags */ 79 * rza1_bidir_pin - describe a single pin that needs bidir flag applied. 82 u8 pin: 4; member 96 * rza1_swio_pin - describe a single pin that needs bidir flag applied. 99 u16 pin: 4; member 126 { .pin = 0, .func = 1 }, [all …]
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/Linux-v5.4/arch/arm64/boot/dts/actions/ |
D | s900-bubblegum-96.dts | 48 * NC = not connected (pin out but not routed from the chip to 50 * "[PER]" = pin is muxed for [peripheral] (not GPIO) 73 "GPIO-A", /* GPIO_0, LSEC pin 23 */ 74 "GPIO-B", /* GPIO_1, LSEC pin 24 */ 75 "GPIO-C", /* GPIO_2, LSEC pin 25 */ 76 "GPIO-D", /* GPIO_3, LSEC pin 26 */ 77 "GPIO-E", /* GPIO_4, LSEC pin 27 */ 78 "GPIO-F", /* GPIO_5, LSEC pin 28 */ 79 "GPIO-G", /* GPIO_6, LSEC pin 29 */ 80 "GPIO-H", /* GPIO_7, LSEC pin 30 */ [all …]
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/Linux-v5.4/drivers/pinctrl/sh-pfc/ |
D | Kconfig | 7 bool "Renesas SoC pin control support" if COMPILE_TEST && !(ARCH_RENESAS || SUPERH) 49 This enables pin control drivers for Renesas SuperH and ARM platforms 55 This enables pin control and GPIO drivers for SH/SH Mobile platforms 64 bool "Emma Mobile AV2 pin control support" if COMPILE_TEST 67 bool "R-Mobile APE6 pin control support" if COMPILE_TEST 71 bool "R-Mobile A1 pin control support" if COMPILE_TEST 75 bool "RZ/G1M pin control support" if COMPILE_TEST 78 bool "RZ/G1N pin control support" if COMPILE_TEST 81 bool "RZ/G1E pin control support" if COMPILE_TEST 84 bool "RZ/G1C pin control support" if COMPILE_TEST [all …]
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