| /Linux-v6.1/Documentation/devicetree/bindings/usb/ |
| D | amlogic,meson-g12a-usb-ctrl.yaml | 112 - const: usb2-phy0 # USB2 PHY0 if USBHOST_A port is used
114 - const: usb3-phy0 # USB3 PHY if USB3_0 is used
131 - const: usb2-phy0 # USB2 PHY0 if USBHOST_A port is used
151 - const: usb2-phy0 # USB2 PHY0 if USBHOST_A port is used
213 phy-names = "usb2-phy0", "usb2-phy1", "usb3-phy0";
|
| /Linux-v6.1/drivers/phy/allwinner/ |
| D | phy-sun4i-usb.c | 82 /* A83T specific control bits for PHY0 */
141 /* phy0 / otg related variables */
434 /* For phy0 only turn on Vbus if we don't have an ext. Vbus */ in sun4i_usb_phy_power_on()
466 * phy0 vbus typically slowly discharges, sometimes this causes the in sun4i_usb_phy_power_off()
537 /* Host mode. Route phy0 to EHCI/OHCI */ in sun4i_usb_phy0_reroute()
540 /* Peripheral mode. Route phy0 to MUSB */ in sun4i_usb_phy0_reroute()
550 struct phy *phy0 = data->phys[0].phy; in sun4i_usb_phy0_id_vbus_det_scan() local
555 if (!phy0) in sun4i_usb_phy0_id_vbus_det_scan()
558 phy = phy_get_drvdata(phy0); in sun4i_usb_phy0_id_vbus_det_scan()
562 mutex_lock(&phy0->mutex); in sun4i_usb_phy0_id_vbus_det_scan()
[all …]
|
| /Linux-v6.1/arch/arm64/boot/dts/broadcom/stingray/ |
| D | stingray-usb.dtsi | 29 phy-names = "phy0", "phy1";
39 phy-names = "phy0", "phy1";
63 phy-names = "phy0", "phy1", "phy2";
73 phy-names = "phy0";
|
| /Linux-v6.1/Documentation/devicetree/bindings/clock/ |
| D | qcom,sm8450-dispcc.yaml | 31 - description: Byte clock from DSI PHY0
32 - description: Pixel clock from DSI PHY0
35 - description: Link clock from DP PHY0
36 - description: VCO DIV clock from DP PHY0
|
| D | qcom,sm6115-dispcc.yaml | 28 - description: Byte clock from DSI PHY0
29 - description: Pixel clock from DSI PHY0
|
| D | qcom,gcc-msm8976.yaml | 30 - description: Pixel clock from DSI PHY0
31 - description: Byte clock from DSI PHY0
|
| /Linux-v6.1/Documentation/devicetree/bindings/net/ |
| D | qcom-emac.txt | 48 phy-handle = <&phy0>;
52 phy0: ethernet-phy@0 {
97 phy-handle = <&phy0>;
101 phy0: ethernet-phy@4 {
|
| D | arc_emac.txt | 39 phy = <&phy0>;
43 phy0: ethernet-phy@0 {
|
| /Linux-v6.1/arch/arm64/boot/dts/freescale/ |
| D | fsl-ls1028a-kontron-sl28-var1.dts | 28 phy0: ethernet-phy@4 { label
51 /* Delete the phy-handle to the old phy0 label */
56 phy-handle = <&phy0>;
|
| /Linux-v6.1/arch/riscv/boot/dts/microchip/ |
| D | mpfs-polarberry.dts | 41 * phy0 is connected to mac0, but the port itself is on the (optional) carrier
46 phy-handle = <&phy0>;
59 phy0: ethernet-phy@4 { label
|
| /Linux-v6.1/arch/arm64/boot/dts/marvell/ |
| D | armada-8040-mcbin.dts | 20 phy0: ethernet-phy@0 { label
36 phy = <&phy0>;
|
| /Linux-v6.1/arch/arm/boot/dts/ |
| D | rk3036-evb.dts | 18 phy = <&phy0>;
29 phy0: ethernet-phy@0 { label
|
| D | stm32mp151a-prtt1a.dts | 16 phy-handle = <&phy0>;
21 phy0: ethernet-phy@0 { label
|
| D | stm32mp151a-prtt1s.dts | 16 phy-handle = <&phy0>;
55 phy0: ethernet-phy@0 { label
|
| D | intel-ixp42x-ixdp425.dts | 47 phy-handle = <&phy0>;
53 phy0: ethernet-phy@0 { label
|
| D | am335x-moxa-uc-2101.dts | 56 phy0: ethernet-phy@4 { label
62 phy-handle = <&phy0>;
|
| /Linux-v6.1/arch/arm64/boot/dts/toshiba/ |
| D | tmpv7708-visrobo-vrb.dts | 43 phy-handle = <&phy0>;
50 phy0: ethernet-phy@1 { label
|
| D | tmpv7708-rm-mbrc.dts | 43 phy-handle = <&phy0>;
50 phy0: ethernet-phy@1 { label
|
| /Linux-v6.1/arch/arm64/boot/dts/renesas/ |
| D | cat875.dtsi | 20 phy-handle = <&phy0>;
24 phy0: ethernet-phy@0 { label
|
| D | hihope-rzg2-ex.dtsi | 21 phy-handle = <&phy0>;
26 phy0: ethernet-phy@0 { label
|
| D | r8a779a0-falcon.dts | 25 phy-handle = <&phy0>;
29 phy0: ethernet-phy@0 { label
|
| D | r9a09g011-v2mevk2.dts | 42 phy-handle = <&phy0>;
46 phy0: ethernet-phy@0 { label
|
| /Linux-v6.1/drivers/staging/media/max96712/ |
| D | max96712.c | 130 /* Configure a 4-lane DPHY using PHY0 and PHY1. */ in max96712_mipi_configure()
135 /* Configure lane mapping for PHY0 and PHY1. */ in max96712_mipi_configure()
139 /* Configure lane polarity for PHY0 and PHY1. */ in max96712_mipi_configure()
145 /* Set link frequency for PHY0 and PHY1. */ in max96712_mipi_configure()
151 /* Enable PHY0 and PHY1 */ in max96712_mipi_configure()
|
| /Linux-v6.1/arch/powerpc/boot/dts/ |
| D | cm5200.dts | 51 phy-handle = <&phy0>;
55 phy0: ethernet-phy@0 { label
|
| /Linux-v6.1/Documentation/devicetree/bindings/phy/ |
| D | nvidia,tegra20-usb-phy.yaml | 32 PHY0 and PHY2 share power and ground, PHY0 contains shared registers.
33 PHY0 and PHY2 must specify two register sets, where the first set is
34 PHY own registers and the second set is the PHY0 registers.
|
