Home
last modified time | relevance | path

Searched +full:phy +full:- +full:mode (Results 1 – 25 of 1048) sorted by relevance

12345678910>>...42

/Linux-v5.15/arch/arm64/boot/dts/microchip/
Dsparx5_pcb135_board.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
10 gpio-restart {
11 compatible = "gpio-restart";
17 compatible = "gpio-leds";
21 default-state = "off";
26 default-state = "off";
31 default-state = "off";
36 default-state = "off";
41 default-state = "off";
[all …]
/Linux-v5.15/drivers/nfc/s3fwrn5/
Dphy_common.c1 // SPDX-License-Identifier: GPL-2.0-or-later
19 struct phy_common *phy = phy_id; in s3fwrn5_phy_set_wake() local
21 mutex_lock(&phy->mutex); in s3fwrn5_phy_set_wake()
22 gpio_set_value(phy->gpio_fw_wake, wake); in s3fwrn5_phy_set_wake()
25 mutex_unlock(&phy->mutex); in s3fwrn5_phy_set_wake()
29 bool s3fwrn5_phy_power_ctrl(struct phy_common *phy, enum s3fwrn5_mode mode) in s3fwrn5_phy_power_ctrl() argument
31 if (phy->mode == mode) in s3fwrn5_phy_power_ctrl()
34 phy->mode = mode; in s3fwrn5_phy_power_ctrl()
36 gpio_set_value(phy->gpio_en, 1); in s3fwrn5_phy_power_ctrl()
37 gpio_set_value(phy->gpio_fw_wake, 0); in s3fwrn5_phy_power_ctrl()
[all …]
Di2c.c1 // SPDX-License-Identifier: GPL-2.0-or-later
31 static void s3fwrn5_i2c_set_mode(void *phy_id, enum s3fwrn5_mode mode) in s3fwrn5_i2c_set_mode() argument
33 struct s3fwrn5_i2c_phy *phy = phy_id; in s3fwrn5_i2c_set_mode() local
35 mutex_lock(&phy->common.mutex); in s3fwrn5_i2c_set_mode()
37 if (s3fwrn5_phy_power_ctrl(&phy->common, mode) == false) in s3fwrn5_i2c_set_mode()
40 phy->irq_skip = true; in s3fwrn5_i2c_set_mode()
43 mutex_unlock(&phy->common.mutex); in s3fwrn5_i2c_set_mode()
48 struct s3fwrn5_i2c_phy *phy = phy_id; in s3fwrn5_i2c_write() local
51 mutex_lock(&phy->common.mutex); in s3fwrn5_i2c_write()
53 phy->irq_skip = false; in s3fwrn5_i2c_write()
[all …]
/Linux-v5.15/drivers/gpu/drm/hisilicon/kirin/
Ddw_drm_dsi.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * Copyright (c) 2014-2016 HiSilicon Limited.
88 struct mipi_phy_params phy; member
121 static u32 dsi_calc_phy_rate(u32 req_kHz, struct mipi_phy_params *phy) in dsi_calc_phy_rate() argument
151 phy->pll_vco_750M = dphy_range_info[i].pll_vco_750M; in dsi_calc_phy_rate()
152 phy->hstx_ckg_sel = dphy_range_info[i].hstx_ckg_sel; in dsi_calc_phy_rate()
154 if (phy->hstx_ckg_sel <= 7 && in dsi_calc_phy_rate()
155 phy->hstx_ckg_sel >= 4) in dsi_calc_phy_rate()
156 q_pll = 0x10 >> (7 - phy->hstx_ckg_sel); in dsi_calc_phy_rate()
190 phy->pll_fbd_p = 0; in dsi_calc_phy_rate()
[all …]
/Linux-v5.15/drivers/phy/marvell/
Dphy-mvebu-a3700-comphy.c1 // SPDX-License-Identifier: GPL-2.0
9 * Structure inspired from phy-mvebu-cp110-comphy.c written by Antoine Tenart.
13 #include <linux/arm-smccc.h>
18 #include <linux/phy.h>
19 #include <linux/phy/phy.h>
40 #define COMPHY_FW_SPEED_3_125G 2 /* 2500BASE-X */
44 #define COMPHY_FW_MODE(mode) ((mode) << 12) argument
45 #define COMPHY_FW_NET(mode, idx, speed) (COMPHY_FW_MODE(mode) | \ argument
48 #define COMPHY_FW_PCIE(mode, idx, speed, width) (COMPHY_FW_NET(mode, idx, speed) | \ argument
53 enum phy_mode mode; member
[all …]
/Linux-v5.15/drivers/phy/hisilicon/
Dphy-histb-combphy.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2016-2017 HiSilicon Co., Ltd. http://www.hisilicon.com
17 #include <linux/phy/phy.h>
20 #include <dt-bindings/phy/phy.h>
48 struct phy *phy; member
49 struct histb_combphy_mode mode; member
55 void __iomem *reg = priv->mmio + COMBPHY_CFG_REG; in nano_register_write()
73 static int is_mode_fixed(struct histb_combphy_mode *mode) in is_mode_fixed() argument
75 return (mode->fixed != PHY_NONE) ? true : false; in is_mode_fixed()
80 struct histb_combphy_mode *mode = &priv->mode; in histb_combphy_set_mode() local
[all …]
/Linux-v5.15/include/linux/phy/
Dphy.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * phy.h -- generic phy header file
5 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
19 #include <linux/phy/phy-dp.h>
20 #include <linux/phy/phy-mipi-dphy.h>
22 struct phy;
54 * union phy_configure_opts - Opaque generic phy configuration
57 * the MIPI_DPHY phy mode.
67 * struct phy_ops - set of function pointers for performing phy operations
68 * @init: operation to be performed for initializing phy
[all …]
/Linux-v5.15/drivers/phy/ti/
Dphy-ti-pipe3.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * phy-ti-pipe3 - PIPE3 PHY driver.
5 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
12 #include <linux/phy/phy.h>
19 #include <linux/phy/omap_control_phy.h>
181 enum pipe3_mode mode; member
206 enum pipe3_mode mode; member
212 .mode = PIPE3_MODE_USBSS,
215 /* DRA75x TRM Table 26-17 Preferred USB3_PHY_RX SCP Register Settings */
238 .mode = PIPE3_MODE_SATA,
[all …]
/Linux-v5.15/Documentation/devicetree/bindings/phy/
Dphy-hi3798cv200-combphy.txt1 HiSilicon STB PCIE/SATA/USB3 PHY
4 - compatible: Should be "hisilicon,hi3798cv200-combphy"
5 - reg: Should be the address space for COMBPHY configuration and state
8 - #phy-cells: Should be 1. The cell number is used to select the phy mode
9 as defined in <dt-bindings/phy/phy.h>.
10 - clocks: The phandle to clock provider and clock specifier pair.
11 - resets: The phandle to reset controller and reset specifier pair.
13 Refer to phy/phy-bindings.txt for the generic PHY binding properties.
16 - hisilicon,fixed-mode: If the phy device doesn't support mode select
17 but a fixed mode setting, the property should be present to specify
[all …]
Dti,phy-gmii-sel.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
4 ---
5 $id: "http://devicetree.org/schemas/phy/ti,phy-gmii-sel.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
8 title: CPSW Port's Interface Mode Selection PHY Tree Bindings
11 - Kishon Vijay Abraham I <kishon@ti.com>
16 The interface mode is selected by configuring the MII mode selection register(s)
20 +--------------+
21 +-------------------------------+ |SCM |
[all …]
/Linux-v5.15/arch/mips/boot/dts/mscc/
Docelot_pcb120.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
4 /dts-v1/;
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/interrupt-controller/irq.h>
8 #include <dt-bindings/phy/phy-ocelot-serdes.h>
12 compatible = "mscc,ocelot-pcb120", "mscc,ocelot";
15 stdout-path = "serial0:115200n8";
42 pinctrl-names = "default";
43 pinctrl-0 = <&miim1>, <&phy_int_pins>, <&phy_load_save_pins>;
45 phy7: ethernet-phy@0 {
[all …]
/Linux-v5.15/drivers/phy/amlogic/
Dphy-meson-gxl-usb2.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Meson GXL and GXM USB2 PHY driver
15 #include <linux/phy/phy.h>
18 /* bits [31:27] are read-only */
66 /* bits [31:14] are read-only */
94 enum phy_mode mode; member
107 static int phy_meson_gxl_usb2_init(struct phy *phy) in phy_meson_gxl_usb2_init() argument
109 struct phy_meson_gxl_usb2_priv *priv = phy_get_drvdata(phy); in phy_meson_gxl_usb2_init()
112 ret = reset_control_reset(priv->reset); in phy_meson_gxl_usb2_init()
116 ret = clk_prepare_enable(priv->clk); in phy_meson_gxl_usb2_init()
[all …]
Dphy-meson-g12a-usb3-pcie.c1 // SPDX-License-Identifier: GPL-2.0
3 * Amlogic G12A USB3 + PCIE Combo PHY driver
15 #include <linux/phy/phy.h>
19 #include <dt-bindings/phy/phy.h>
60 struct phy *phy; member
61 unsigned int mode; member
79 regmap_write(priv->regmap, PHY_R4, reg); in phy_g12a_usb3_pcie_cr_bus_addr()
80 regmap_write(priv->regmap, PHY_R4, reg); in phy_g12a_usb3_pcie_cr_bus_addr()
82 regmap_write(priv->regmap, PHY_R4, reg | PHY_R4_PHY_CR_CAP_ADDR); in phy_g12a_usb3_pcie_cr_bus_addr()
84 ret = regmap_read_poll_timeout(priv->regmap, PHY_R5, val, in phy_g12a_usb3_pcie_cr_bus_addr()
[all …]
/Linux-v5.15/Documentation/devicetree/bindings/net/dsa/
Dmt7530.txt6 - compatible: may be compatible = "mediatek,mt7530"
9 - #address-cells: Must be 1.
10 - #size-cells: Must be 0.
11 - mediatek,mcm: Boolean; if defined, indicates that either MT7530 is the part
12 on multi-chip module belong to MT7623A has or the remotely standalone
17 - core-supply: Phandle to the regulator node necessary for the core power.
18 - io-supply: Phandle to the regulator node necessary for the I/O power.
19 See Documentation/devicetree/bindings/regulator/mt6323-regulator.txt
24 - reset-gpios: Should be a gpio specifier for a reset line.
28 - resets : Phandle pointing to the system reset controller with
[all …]
Dqca8k.txt5 - compatible: should be one of:
10 - #size-cells: must be 0
11 - #address-cells: must be 1
15 - reset-gpios: GPIO to be used to reset the whole device
21 mdio-bus each subnode describing a port needs to have a valid phandle
22 referencing the internal PHY it is connected to. This is because there's no
23 N:N mapping of port and PHY id.
24 To declare the internal mdio-bus configuration, declare a mdio node in the
26 PHY is connected to. In this config a internal mdio-bus is registered and
29 Don't use mixed external and internal mdio-bus configurations, as this is
[all …]
Dar9331.txt1 Atheros AR9331 built-in switch
4 It is a switch built-in to Atheros AR9331 WiSoC and addressable over internal
5 MDIO bus. All PHYs are built-in as well.
9 - compatible: should be: "qca,ar9331-switch"
10 - reg: Address on the MII bus for the switch.
11 - resets : Must contain an entry for each entry in reset-names.
12 - reset-names : Must include the following entries: "switch"
13 - interrupt-parent: Phandle to the parent interrupt controller
14 - interrupts: IRQ line for the switch
15 - interrupt-controller: Indicates the switch is itself an interrupt
[all …]
/Linux-v5.15/arch/powerpc/boot/dts/fsl/
Dt1040rdb.dts4 * Copyright 2014 - 2015 Freescale Semiconductor Inc.
35 /include/ "t104xsi-pre.dtsi"
49 fixed-link = <0 1 1000 0 0>;
50 phy-connection-type = "sgmii";
54 fixed-link = <1 1 1000 0 0>;
55 phy-connection-type = "sgmii";
59 phy-handle = <&phy_sgmii_2>;
60 phy-connection-type = "sgmii";
64 phy_sgmii_2: ethernet-phy@3 {
68 /* VSC8514 QSGMII PHY */
[all …]
/Linux-v5.15/Documentation/devicetree/bindings/net/
Dti,dp83822.yaml1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
4 ---
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
8 title: TI DP83822 ethernet PHY
11 - Dan Murphy <dmurphy@ti.com>
14 The DP83822 is a low-power, single-port, 10/100 Mbps Ethernet PHY. It
16 data over standard, twisted-pair cables or to connect to an external,
17 fiber-optic transceiver. Additionally, the DP83822 provides flexibility to
20 Specifications about the Ethernet PHY can be found at:
24 - $ref: "ethernet-phy.yaml#"
[all …]
Dqca,ar71xx.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - $ref: ethernet-controller.yaml#
13 - Oleksij Rempel <o.rempel@pengutronix.de>
18 - items:
19 - enum:
20 - qca,ar7100-eth # Atheros AR7100
21 - qca,ar7240-eth # Atheros AR7240
22 - qca,ar7241-eth # Atheros AR7241
[all …]
Dadi,adin.yaml1 # SPDX-License-Identifier: GPL-2.0+
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Analog Devices ADIN1200/ADIN1300 PHY
10 - Alexandru Ardelean <alexandru.ardelean@analog.com>
16 - $ref: ethernet-phy.yaml#
19 adi,rx-internal-delay-ps:
21 RGMII RX Clock Delay used only when PHY operates in RGMII mode with
22 internal delay (phy-mode is 'rgmii-id' or 'rgmii-rxid') in pico-seconds.
26 adi,tx-internal-delay-ps:
[all …]
/Linux-v5.15/drivers/media/platform/omap3isp/
Dispcsiphy.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * TI OMAP3 ISP - CSI PHY module
23 static void csiphy_routing_cfg_3630(struct isp_csiphy *phy, in csiphy_routing_cfg_3630() argument
28 u32 shift, mode; in csiphy_routing_cfg_3630() local
30 regmap_read(phy->isp->syscon, phy->isp->syscon_offset, &reg); in csiphy_routing_cfg_3630()
41 mode = OMAP3630_CONTROL_CAMERA_PHY_CTRL_CAMMODE_DPHY; in csiphy_routing_cfg_3630()
49 mode = OMAP3630_CONTROL_CAMERA_PHY_CTRL_CAMMODE_DPHY; in csiphy_routing_cfg_3630()
53 /* Select data/clock or data/strobe mode for CCP2 */ in csiphy_routing_cfg_3630()
57 mode = OMAP3630_CONTROL_CAMERA_PHY_CTRL_CAMMODE_CCP2_DATA_STROBE; in csiphy_routing_cfg_3630()
59 mode = OMAP3630_CONTROL_CAMERA_PHY_CTRL_CAMMODE_CCP2_DATA_CLOCK; in csiphy_routing_cfg_3630()
[all …]
/Linux-v5.15/drivers/net/
Dsungem_phy.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * PHY drivers for the sungem ethernet driver.
7 * (c) 2002-2007, Benjamin Herrenscmidt (benh@kernel.crashing.org)
10 * - Add support for PHYs that provide an IRQ line
11 * - Eventually moved the entire polling state machine in
14 * - On LXT971 & BCM5201, Apple uses some chip specific regs
17 * - Apple has some additional power management code for some
39 /* Link modes of the BCM5400 PHY */
51 static inline int __sungem_phy_read(struct mii_phy* phy, int id, int reg) in __sungem_phy_read() argument
53 return phy->mdio_read(phy->dev, id, reg); in __sungem_phy_read()
[all …]
/Linux-v5.15/drivers/phy/st/
Dphy-spear1340-miphy.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * ST spear1340-miphy driver
12 #include <linux/dma-mapping.h>
17 #include <linux/phy/phy.h>
32 /* PCIE - SATA configuration registers */
80 /* phy mode: 0 for SATA 1 for PCIe */
81 enum spear1340_miphy_mode mode; member
84 /* phy struct pointer */
85 struct phy *phy; member
90 regmap_update_bits(priv->misc, SPEAR1340_PCIE_SATA_CFG, in spear1340_miphy_sata_init()
[all …]
/Linux-v5.15/drivers/usb/phy/
Dphy-ab8500-usb.c1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright (C) 2010-2013 ST-Ericsson AB
22 #include <linux/usb/musb-ux500.h>
121 /* Driver is using the ab-iddet driver*/
127 struct usb_phy phy; member
132 enum ab8500_usb_mode mode; member
147 return container_of(x, struct ab8500_usb, phy); in phy_to_ab()
152 abx500_set_register_interruptible(ab->dev, in ab8500_usb_wd_workaround()
159 abx500_set_register_interruptible(ab->dev, in ab8500_usb_wd_workaround()
167 abx500_set_register_interruptible(ab->dev, in ab8500_usb_wd_workaround()
[all …]
/Linux-v5.15/drivers/net/ethernet/ti/
Dcpsw-phy-sel.c1 // SPDX-License-Identifier: GPL-2.0
13 #include <linux/phy.h>
45 u32 mode = 0; in cpsw_gmii_sel_am3352() local
48 reg = readl(priv->gmii_sel); in cpsw_gmii_sel_am3352()
52 mode = AM33XX_GMII_SEL_MODE_RMII; in cpsw_gmii_sel_am3352()
56 mode = AM33XX_GMII_SEL_MODE_RGMII; in cpsw_gmii_sel_am3352()
62 mode = AM33XX_GMII_SEL_MODE_RGMII; in cpsw_gmii_sel_am3352()
67 dev_warn(priv->dev, in cpsw_gmii_sel_am3352()
68 "Unsupported PHY mode: \"%s\". Defaulting to MII.\n", in cpsw_gmii_sel_am3352()
72 mode = AM33XX_GMII_SEL_MODE_MII; in cpsw_gmii_sel_am3352()
[all …]

12345678910>>...42