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/Linux-v5.4/drivers/clk/hisilicon/
Dclk-hisi-phase.c5 * Simple HiSilicon phase clock implementation.
30 static int hisi_phase_regval_to_degrees(struct clk_hisi_phase *phase, in hisi_phase_regval_to_degrees() argument
35 for (i = 0; i < phase->phase_num; i++) in hisi_phase_regval_to_degrees()
36 if (phase->phase_regvals[i] == regval) in hisi_phase_regval_to_degrees()
37 return phase->phase_degrees[i]; in hisi_phase_regval_to_degrees()
44 struct clk_hisi_phase *phase = to_clk_hisi_phase(hw); in hisi_clk_get_phase() local
47 regval = readl(phase->reg); in hisi_clk_get_phase()
48 regval = (regval & phase->mask) >> phase->shift; in hisi_clk_get_phase()
50 return hisi_phase_regval_to_degrees(phase, regval); in hisi_clk_get_phase()
53 static int hisi_phase_degrees_to_regval(struct clk_hisi_phase *phase, in hisi_phase_degrees_to_regval() argument
[all …]
/Linux-v5.4/drivers/clk/sunxi-ng/
Dccu_phase.c15 struct ccu_phase *phase = hw_to_ccu_phase(hw); in ccu_phase_get_phase() local
22 reg = readl(phase->common.base + phase->common.reg); in ccu_phase_get_phase()
23 delay = (reg >> phase->shift); in ccu_phase_get_phase()
24 delay &= (1 << phase->width) - 1; in ccu_phase_get_phase()
58 struct ccu_phase *phase = hw_to_ccu_phase(hw); in ccu_phase_set_phase() local
110 spin_lock_irqsave(phase->common.lock, flags); in ccu_phase_set_phase()
111 reg = readl(phase->common.base + phase->common.reg); in ccu_phase_set_phase()
112 reg &= ~GENMASK(phase->width + phase->shift - 1, phase->shift); in ccu_phase_set_phase()
113 writel(reg | (delay << phase->shift), in ccu_phase_set_phase()
114 phase->common.base + phase->common.reg); in ccu_phase_set_phase()
[all …]
/Linux-v5.4/drivers/clk/meson/
Dclk-phase.c11 #include "clk-phase.h"
40 struct meson_clk_phase_data *phase = meson_clk_phase_data(clk); in meson_clk_phase_get_phase() local
43 val = meson_parm_read(clk->map, &phase->ph); in meson_clk_phase_get_phase()
45 return meson_clk_degrees_from_val(val, phase->ph.width); in meson_clk_phase_get_phase()
51 struct meson_clk_phase_data *phase = meson_clk_phase_data(clk); in meson_clk_phase_set_phase() local
54 val = meson_clk_degrees_to_val(degrees, phase->ph.width); in meson_clk_phase_set_phase()
55 meson_parm_write(clk->map, &phase->ph, val); in meson_clk_phase_set_phase()
68 * The phase of mst_sclk clock output can be controlled independently
72 * If necessary, we can still control the phase in the tdm block
87 /* Get phase 0 and sync it to phase 1 and 2 */ in meson_clk_triphase_sync()
[all …]
/Linux-v5.4/drivers/clk/sunxi/
Dclk-mod0.c175 struct mmc_phase *phase = to_mmc_phase(hw); in mmc_get_phase() local
181 value = readl(phase->reg); in mmc_get_phase()
182 delay = (value >> phase->offset) & 0x3; in mmc_get_phase()
217 struct mmc_phase *phase = to_mmc_phase(hw); in mmc_set_phase() local
268 spin_lock_irqsave(phase->lock, flags); in mmc_set_phase()
269 value = readl(phase->reg); in mmc_set_phase()
270 value &= ~GENMASK(phase->offset + 3, phase->offset); in mmc_set_phase()
271 value |= delay << phase->offset; in mmc_set_phase()
272 writel(value, phase->reg); in mmc_set_phase()
273 spin_unlock_irqrestore(phase->lock, flags); in mmc_set_phase()
[all …]
/Linux-v5.4/drivers/mmc/host/
Dsdhci-sirf.c77 int phase; in sdhci_sirf_execute_tuning() local
88 phase = 0; in sdhci_sirf_execute_tuning()
92 clock_setting | phase, in sdhci_sirf_execute_tuning()
98 dev_dbg(mmc_dev(mmc), "%s: Found good phase = %d\n", in sdhci_sirf_execute_tuning()
99 mmc_hostname(mmc), phase); in sdhci_sirf_execute_tuning()
101 start = phase; in sdhci_sirf_execute_tuning()
102 end = phase; in sdhci_sirf_execute_tuning()
104 if (phase == (SIRF_TUNING_COUNT - 1) in sdhci_sirf_execute_tuning()
108 dev_dbg(mmc_dev(mmc), "%s: Found bad phase = %d\n", in sdhci_sirf_execute_tuning()
109 mmc_hostname(mmc), phase); in sdhci_sirf_execute_tuning()
[all …]
Ddw_mmc-rockchip.c68 * Set the drive phase offset based on speed mode to achieve hold times. in dw_mci_rk3288_set_ios()
94 int phase; in dw_mci_rk3288_set_ios() local
97 * In almost all cases a 90 degree phase offset will provide in dw_mci_rk3288_set_ios()
102 phase = 90; in dw_mci_rk3288_set_ios()
108 * bus width is 8 we need to double the phase offset in dw_mci_rk3288_set_ios()
112 phase = 180; in dw_mci_rk3288_set_ios()
124 phase = 180; in dw_mci_rk3288_set_ios()
128 clk_set_phase(priv->drv_clk, phase); in dw_mci_rk3288_set_ios()
163 /* Try each phase and extract good ranges */ in dw_mci_rk3288_execute_tuning()
213 dev_info(host->dev, "All phases work, using default phase %d.", in dw_mci_rk3288_execute_tuning()
[all …]
/Linux-v5.4/drivers/gpu/drm/amd/display/dc/dce/
Ddce_clock_source.h61 SRII(PHASE, DP_DTO, 0),\
62 SRII(PHASE, DP_DTO, 1),\
63 SRII(PHASE, DP_DTO, 2),\
64 SRII(PHASE, DP_DTO, 3),\
65 SRII(PHASE, DP_DTO, 4),\
66 SRII(PHASE, DP_DTO, 5),\
84 SRII(PHASE, DP_DTO, 0),\
85 SRII(PHASE, DP_DTO, 1),\
86 SRII(PHASE, DP_DTO, 2),\
87 SRII(PHASE, DP_DTO, 3),\
[all …]
/Linux-v5.4/Documentation/devicetree/bindings/mmc/
Dexynos-dw-mshc.txt30 * samsung,dw-mshc-sdr-timing: Specifies the value of CIU clock phase shift value
31 in transmit mode and CIU clock phase shift value in receive mode for single
35 * samsung,dw-mshc-ddr-timing: Specifies the value of CUI clock phase shift value
36 in transmit mode and CIU clock phase shift value in receive mode for double
39 * samsung,dw-mshc-hs400-timing: Specifies the value of CIU TX and RX clock phase
45 - First Cell: CIU clock phase shift value for tx mode.
46 - Second Cell: CIU clock phase shift value for rx mode.
49 - valid value for tx phase shift and rx phase shift is 0 to 7.
50 - when CIU clock divider value is set to 3, all possible 8 phase shift
53 phase shift clocks should be 0.
/Linux-v5.4/drivers/char/
Dppdev.c20 * SETPHASE set the IEEE 1284 phase of a particular mode. Not to be
37 * GETPHASE gets the current IEEE1284 phase
392 pp->saved_state.phase = info->phase; in pp_do_ioctl()
394 info->phase = pp->state.phase; in pp_do_ioctl()
423 pp->state.phase = init_phase(mode); in pp_do_ioctl()
427 pp->pdev->port->ieee1284.phase = pp->state.phase; in pp_do_ioctl()
447 int phase; in pp_do_ioctl() local
449 if (copy_from_user(&phase, argp, sizeof(phase))) in pp_do_ioctl()
452 /* FIXME: validate phase */ in pp_do_ioctl()
453 pp->state.phase = phase; in pp_do_ioctl()
[all …]
/Linux-v5.4/drivers/media/i2c/
Dsaa711x_regs.h112 /* Horizontal phase scaling */
159 /* Horizontal phase scaling */
422 /* Task A: Horizontal phase scaling */
426 "Task A: Horizontal luminance phase offset"},
431 "Task A: Horizontal chrominance phase offset"},
443 "Task A: Vertical chrominance phase offset '00'"},
445 "Task A: Vertical chrominance phase offset '01'"},
447 "Task A: Vertical chrominance phase offset '10'"},
449 "Task A: Vertical chrominance phase offset '11'"},
451 "Task A: Vertical luminance phase offset '00'"},
[all …]
/Linux-v5.4/include/trace/events/
Dclk.h156 TP_PROTO(struct clk_core *core, int phase),
158 TP_ARGS(core, phase),
162 __field( int, phase )
167 __entry->phase = phase;
170 TP_printk("%s %d", __get_str(name), (int)__entry->phase)
175 TP_PROTO(struct clk_core *core, int phase),
177 TP_ARGS(core, phase)
182 TP_PROTO(struct clk_core *core, int phase),
184 TP_ARGS(core, phase)
/Linux-v5.4/drivers/staging/iio/Documentation/
Dsysfs-bus-iio-dds36 Stores phase into Y.
38 allows for pin controlled PSK Phase Shift Keying
40 control the desired phase Y which is added to the phase
48 the desired value in rad. If shared across all phase registers
56 Specifies the active phase Y which is added to the phase
68 phase is controlled by the respective phase and frequency
/Linux-v5.4/drivers/scsi/
DNCR5380.c74 * phase goes through the various phases as instructed by the target.
245 {BASR_PHASE_MATCH, "PHASE MATCH"},
324 * NCR5380_print_phase - show SCSI phase
327 * Print the current SCSI phase for debugging purposes
338 shost_printk(KERN_DEBUG, instance, "REQ not asserted, phase unknown.\n"); in NCR5380_print_phase()
343 shost_printk(KERN_DEBUG, instance, "phase %s\n", phases[i].name); in NCR5380_print_phase()
448 * the SCSI bus busy. Check for BUS FREE phase. If not, try to abort the
733 * Called by the interrupt handler when DMA finishes or a phase
747 p = hostdata->connected->SCp.phase; in NCR5380_dma_complete()
771 pr_err("scsi%d: bus stuck in data phase -- probably a single byte overrun!\n", in NCR5380_dma_complete()
[all …]
Dmac53c94.c54 enum fsc_phase phase; /* what we're currently trying to do */ member
97 if (state->phase == idle) in mac53c94_queue_lck()
153 if (state->phase != idle || state->current_req != NULL) in mac53c94_start()
178 state->phase = selecting; in mac53c94_start()
212 printk(KERN_DEBUG "mac53c94_intr, intr=%x stat=%x seq=%x phase=%d\n", in mac53c94_interrupt()
213 intr, stat, seq, state->phase); in mac53c94_interrupt()
225 printk(KERN_ERR "53c94: invalid cmd, intr=%x stat=%x seq=%x phase=%d\n", in mac53c94_interrupt()
226 intr, stat, seq, state->phase); in mac53c94_interrupt()
233 printk("53c94: bad error, intr=%x stat=%x seq=%x phase=%d\n", in mac53c94_interrupt()
234 intr, stat, seq, state->phase); in mac53c94_interrupt()
[all …]
Dmesh.c96 u8 phase; member
153 enum mesh_phase phase; /* what we're currently trying to do */ member
222 tlp->phase = (ms->msgphase << 4) + ms->phase; in dlog()
253 t, lp->bs1, lp->bs0, lp->phase); in dumplog()
278 lp->bs1, lp->bs0, lp->phase, lp->tgt); in dumpslog()
322 printk(KERN_DEBUG " phase=%d msgphase=%d conn_tgt=%d data_ptr=%d\n", in mesh_dump_regs()
323 ms->phase, ms->msgphase, ms->conn_tgt, ms->data_ptr); in mesh_dump_regs()
400 ms->phase = idle; in mesh_init()
428 ms->phase = arbitrating; in mesh_start_cmd()
468 if (ms->phase != arbitrating) in mesh_start_cmd()
[all …]
/Linux-v5.4/drivers/char/ipmi/
Dkcs_bmc.c90 kcs_bmc->phase = KCS_PHASE_ERROR; in kcs_force_abort()
99 switch (kcs_bmc->phase) { in kcs_bmc_handle_data()
101 kcs_bmc->phase = KCS_PHASE_WRITE_DATA; in kcs_bmc_handle_data()
121 kcs_bmc->phase = KCS_PHASE_WRITE_DONE; in kcs_bmc_handle_data()
143 kcs_bmc->phase = KCS_PHASE_IDLE; in kcs_bmc_handle_data()
155 kcs_bmc->phase = KCS_PHASE_ABORT_ERROR2; in kcs_bmc_handle_data()
162 kcs_bmc->phase = KCS_PHASE_IDLE; in kcs_bmc_handle_data()
181 kcs_bmc->phase = KCS_PHASE_WRITE_START; in kcs_bmc_handle_cmd()
188 if (kcs_bmc->phase != KCS_PHASE_WRITE_DATA) { in kcs_bmc_handle_cmd()
193 kcs_bmc->phase = KCS_PHASE_WRITE_END_CMD; in kcs_bmc_handle_cmd()
[all …]
/Linux-v5.4/Documentation/driver-api/pm/
Ddevices.rst242 always go together, and both are multi-phase operations.
279 sleep states and the hibernation state ("suspend-to-disk"). Each phase involves
280 executing callbacks for every device before the next phase begins. Not all
293 rules are used to determine which callback to execute in the given phase:
326 1. The ``prepare`` phase is meant to prevent races by preventing new
331 suspend-related phases, during the ``prepare`` phase the device
397 4. The ``suspend_noirq`` phase occurs after IRQ handlers have been disabled,
406 an error during the suspend phase by fielding a shared interrupt
436 generally means undoing the actions of the ``suspend_noirq`` phase. If
450 the preceding ``suspend_late`` phase.
[all …]
/Linux-v5.4/Documentation/networking/
Dcops.txt52 dummy -seed -phase 2 -net 2000 -addr 2000.10 -zone "1033"
53 lt0 -seed -phase 1 -net 1000 -addr 1000.50 -zone "1033"
56 eth0 -seed -phase 2 -net 3000 -addr 3000.20 -zone "1033"
57 lt0 -seed -phase 1 -net 1000 -addr 1000.50 -zone "1033"
61 lt0 -seed -phase 1 -net 1000 -addr 1000.10 -zone "LocalTalk1"
62 lt1 -seed -phase 1 -net 2000 -addr 2000.20 -zone "LocalTalk2"
63 eth0 -seed -phase 2 -net 3000 -addr 3000.30 -zone "EtherTalk"
/Linux-v5.4/Documentation/devicetree/bindings/mfd/
Daxp20x.txt126 DCDC2 : DC-DC buck : vin2-supply : poly-phase capable
127 DCDC3 : DC-DC buck : vin3-supply : poly-phase capable
129 DCDC5 : DC-DC buck : vin5-supply : poly-phase capable
130 DCDC6 : DC-DC buck : vin6-supply : poly-phase capable
153 DCDCA : DC-DC buck : vina-supply : poly-phase capable
154 DCDCB : DC-DC buck : vinb-supply : poly-phase capable
155 DCDCC : DC-DC buck : vinc-supply : poly-phase capable
156 DCDCD : DC-DC buck : vind-supply : poly-phase capable
157 DCDCE : DC-DC buck : vine-supply : poly-phase capable
170 Additionally, the AXP806 DC-DC regulators support poly-phase arrangements
[all …]
/Linux-v5.4/drivers/scsi/pcmcia/
Dnsp_message.c20 * NSP invoke interrupts only in the case of scsi phase changes, in nsp_message_in()
21 * therefore we should poll the scsi phase here to catch in nsp_message_in()
22 * the next "msg in" if exists (no scsi phase changes). in nsp_message_in()
61 * NSP invoke interrupts only in the case of scsi phase changes, in nsp_message_out()
62 * therefore we should poll the scsi phase here to catch in nsp_message_out()
63 * the next "msg out" if exists (no scsi phase changes). in nsp_message_out()
Dnsp_cs.c230 SCpnt->SCp.phase = PH_UNDETERMINED; in nsp_queuecommand_lck()
238 SCp.phase : current state of the command */ in nsp_queuecommand_lck()
362 * Start selection phase
371 unsigned char phase, arbit; in nsphw_start_selection() local
375 phase = nsp_index_read(base, SCSIBUSMON); in nsphw_start_selection()
376 if(phase != BUSMON_BUS_FREE) { in nsphw_start_selection()
383 SCpnt->SCp.phase = PH_ARBSTART; in nsphw_start_selection()
403 SCpnt->SCp.phase = PH_SELSTART; in nsphw_start_selection()
514 * wait for bus phase change
550 unsigned char phase, i_src; in nsp_expect_signal() local
[all …]
/Linux-v5.4/drivers/parport/
Dieee1284_ops.c58 port->physport->ieee1284.phase = IEEE1284_PH_FWD_DATA; in parport_ieee1284_write_compat()
144 port->physport->ieee1284.phase = IEEE1284_PH_FWD_IDLE; in parport_ieee1284_write_compat()
177 port->ieee1284.phase = IEEE1284_PH_REV_DATA; in parport_ieee1284_read_nibble()
226 /* Go to reverse idle phase. */ in parport_ieee1284_read_nibble()
230 port->physport->ieee1284.phase = IEEE1284_PH_REV_IDLE; in parport_ieee1284_read_nibble()
233 port->physport->ieee1284.phase = IEEE1284_PH_HBUSY_DAVAIL; in parport_ieee1284_read_nibble()
268 port->physport->ieee1284.phase = IEEE1284_PH_REV_DATA; in parport_ieee1284_read_byte()
314 /* Go to reverse idle phase. */ in parport_ieee1284_read_byte()
318 port->physport->ieee1284.phase = IEEE1284_PH_REV_IDLE; in parport_ieee1284_read_byte()
321 port->physport->ieee1284.phase = IEEE1284_PH_HBUSY_DAVAIL; in parport_ieee1284_read_byte()
[all …]
/Linux-v5.4/drivers/gpu/drm/msm/disp/dpu1/
Ddpu_hw_util.h70 * @ init_phase_x: horizontal initial phase
71 * @ phase_step_x: horizontal phase step
72 * @ init_phase_y: vertical initial phase
73 * @ phase_step_y: vertical phase step
221 * @init_phase_x: Initial scaler phase values for x
222 * @phase_step_x: Phase step values for x
223 * @init_phase_y: Initial scaler phase values for y
224 * @phase_step_y: Phase step values for y
262 * Phase settings
/Linux-v5.4/tools/power/pm-graph/
Dsleepgraph.py1185 # contents: times for phase start/end, order/color data for html
1187 # device callback or action list for this phase
1262 for phase in sorted(self.dmesg.keys()):
1263 if '*' in phase:
1264 p = phase.split('*')
1266 self.dmesg[pnew] = self.dmesg.pop(phase)
1268 for phase in self.sortedPhases():
1269 self.devicegroups.append([phase])
1270 def nextPhase(self, phase, offset): argument
1271 order = self.dmesg[phase]['order'] + offset
[all …]
/Linux-v5.4/drivers/leds/trigger/
Dledtrig-heartbeat.c26 unsigned int phase; member
51 switch (heartbeat_data->phase) { in led_heartbeat_function()
64 heartbeat_data->phase++; in led_heartbeat_function()
70 heartbeat_data->phase++; in led_heartbeat_function()
76 heartbeat_data->phase++; in led_heartbeat_function()
83 heartbeat_data->phase = 0; in led_heartbeat_function()
139 heartbeat_data->phase = 0; in heartbeat_trig_activate()

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