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/Linux-v5.15/drivers/clk/hisilicon/
Dclk-hisi-phase.c5 * Simple HiSilicon phase clock implementation.
30 static int hisi_phase_regval_to_degrees(struct clk_hisi_phase *phase, in hisi_phase_regval_to_degrees() argument
35 for (i = 0; i < phase->phase_num; i++) in hisi_phase_regval_to_degrees()
36 if (phase->phase_regvals[i] == regval) in hisi_phase_regval_to_degrees()
37 return phase->phase_degrees[i]; in hisi_phase_regval_to_degrees()
44 struct clk_hisi_phase *phase = to_clk_hisi_phase(hw); in hisi_clk_get_phase() local
47 regval = readl(phase->reg); in hisi_clk_get_phase()
48 regval = (regval & phase->mask) >> phase->shift; in hisi_clk_get_phase()
50 return hisi_phase_regval_to_degrees(phase, regval); in hisi_clk_get_phase()
53 static int hisi_phase_degrees_to_regval(struct clk_hisi_phase *phase, in hisi_phase_degrees_to_regval() argument
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/Linux-v5.15/drivers/gpu/drm/amd/display/dc/dce/
Ddce_clock_source.h60 SRII(PHASE, DP_DTO, 0),\
61 SRII(PHASE, DP_DTO, 1),\
62 SRII(PHASE, DP_DTO, 2),\
63 SRII(PHASE, DP_DTO, 3),\
64 SRII(PHASE, DP_DTO, 4),\
65 SRII(PHASE, DP_DTO, 5),\
81 SRII(PHASE, DP_DTO, 0),\
82 SRII(PHASE, DP_DTO, 1),\
83 SRII(PHASE, DP_DTO, 2),\
84 SRII(PHASE, DP_DTO, 3),\
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/Linux-v5.15/drivers/clk/sunxi-ng/
Dccu_phase.c15 struct ccu_phase *phase = hw_to_ccu_phase(hw); in ccu_phase_get_phase() local
22 reg = readl(phase->common.base + phase->common.reg); in ccu_phase_get_phase()
23 delay = (reg >> phase->shift); in ccu_phase_get_phase()
24 delay &= (1 << phase->width) - 1; in ccu_phase_get_phase()
58 struct ccu_phase *phase = hw_to_ccu_phase(hw); in ccu_phase_set_phase() local
110 spin_lock_irqsave(phase->common.lock, flags); in ccu_phase_set_phase()
111 reg = readl(phase->common.base + phase->common.reg); in ccu_phase_set_phase()
112 reg &= ~GENMASK(phase->width + phase->shift - 1, phase->shift); in ccu_phase_set_phase()
113 writel(reg | (delay << phase->shift), in ccu_phase_set_phase()
114 phase->common.base + phase->common.reg); in ccu_phase_set_phase()
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/Linux-v5.15/drivers/hwmon/pmbus/
Dmp2888.c3 * Hardware monitoring driver for MPS Multi-phase Digital VR Controllers
83 * Obtain resolution selector for total and phase current report and protection. in mp2888_current_sense_gain_and_resolution_get()
84 * 0: original resolution; 1: half resolution (in such case phase current value should in mp2888_current_sense_gain_and_resolution_get()
94 mp2888_read_phase(struct i2c_client *client, struct mp2888_data *data, int page, int phase, u8 reg) in mp2888_read_phase() argument
98 ret = pmbus_read_word_data(client, page, phase, reg); in mp2888_read_phase()
102 if (!((phase + 1) % 2)) in mp2888_read_phase()
113 * - Rcs is the internal phase current sense resistor. This parameter depends on hardware in mp2888_read_phase()
116 * If phase current resolution bit is set to 1, READ_CSx value should be doubled. in mp2888_read_phase()
117 * Note, that current phase sensing, providing by the device is not accurate. This is in mp2888_read_phase()
129 mp2888_read_phases(struct i2c_client *client, struct mp2888_data *data, int page, int phase) in mp2888_read_phases() argument
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Dmp2975.c3 * Hardware monitoring driver for MPS Multi-phase Digital VR Controllers
90 mp2975_read_word_helper(struct i2c_client *client, int page, int phase, u8 reg, in mp2975_read_word_helper() argument
93 int ret = pmbus_read_word_data(client, page, phase, reg); in mp2975_read_word_helper()
122 int page, int phase, u8 reg) in mp2975_read_phase() argument
126 ret = pmbus_read_word_data(client, page, phase, reg); in mp2975_read_phase()
130 if (!((phase + 1) % MP2975_PAGE_NUM)) in mp2975_read_phase()
141 * - Rcs is the internal phase current sense resistor which is constant in mp2975_read_phase()
147 * Current phase sensing, providing by the device is not accurate in mp2975_read_phase()
150 * case phase current is represented as the maximum between the value in mp2975_read_phase()
153 ret = pmbus_read_word_data(client, page, phase, PMBUS_READ_IOUT); in mp2975_read_phase()
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Dir35221.c25 int phase, int reg) in ir35221_read_word_data() argument
31 ret = pmbus_read_word_data(client, page, phase, in ir35221_read_word_data()
35 ret = pmbus_read_word_data(client, page, phase, in ir35221_read_word_data()
39 ret = pmbus_read_word_data(client, page, phase, in ir35221_read_word_data()
43 ret = pmbus_read_word_data(client, page, phase, in ir35221_read_word_data()
47 ret = pmbus_read_word_data(client, page, phase, in ir35221_read_word_data()
51 ret = pmbus_read_word_data(client, page, phase, in ir35221_read_word_data()
55 ret = pmbus_read_word_data(client, page, phase, in ir35221_read_word_data()
59 ret = pmbus_read_word_data(client, page, phase, in ir35221_read_word_data()
/Linux-v5.15/drivers/clk/sunxi/
Dclk-mod0.c175 struct mmc_phase *phase = to_mmc_phase(hw); in mmc_get_phase() local
181 value = readl(phase->reg); in mmc_get_phase()
182 delay = (value >> phase->offset) & 0x3; in mmc_get_phase()
217 struct mmc_phase *phase = to_mmc_phase(hw); in mmc_set_phase() local
268 spin_lock_irqsave(phase->lock, flags); in mmc_set_phase()
269 value = readl(phase->reg); in mmc_set_phase()
270 value &= ~GENMASK(phase->offset + 3, phase->offset); in mmc_set_phase()
271 value |= delay << phase->offset; in mmc_set_phase()
272 writel(value, phase->reg); in mmc_set_phase()
273 spin_unlock_irqrestore(phase->lock, flags); in mmc_set_phase()
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/Linux-v5.15/drivers/net/wwan/iosm/
Diosm_ipc_imem_ops.c18 ipc_imem_phase_get_string(ipc_imem->phase), if_id); in ipc_imem_sys_wwan_open()
20 /* The network interface is only supported in the runtime phase. */ in ipc_imem_sys_wwan_open()
22 dev_err(ipc_imem->dev, "net:%d : refused phase %s", if_id, in ipc_imem_sys_wwan_open()
23 ipc_imem_phase_get_string(ipc_imem->phase)); in ipc_imem_sys_wwan_open()
71 if (ipc_imem->phase != IPC_P_RUN) { in ipc_imem_sys_wwan_transmit()
72 dev_dbg(ipc_imem->dev, "phase %s transmit", in ipc_imem_sys_wwan_transmit()
73 ipc_imem_phase_get_string(ipc_imem->phase)); in ipc_imem_sys_wwan_transmit()
139 enum ipc_phase phase; in ipc_imem_is_channel_active() local
141 /* Update the current operation phase. */ in ipc_imem_is_channel_active()
142 phase = ipc_imem->phase; in ipc_imem_is_channel_active()
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Diosm_ipc_imem.c155 /* Use the TD update timer only in the runtime phase */ in ipc_imem_td_update_timer_start()
247 ipc_imem_phase_get_string(ipc_imem->phase), in ipc_imem_ipc_init_check()
352 /* Get the internal phase. */ in ipc_imem_ul_pipe_process()
427 /* Consider link power management in the runtime phase. */
446 /* Update & check the current operation phase. */ in ipc_imem_tq_startup_timer_cb()
499 return (ipc_imem->phase == IPC_P_RUN && in ipc_imem_get_exec_stage_buffered()
530 if (ipc_imem->phase != IPC_P_RUN) { in ipc_imem_run_state_worker()
572 enum ipc_phase old_phase, phase; in ipc_imem_handle_irq() local
580 /* Get the internal phase. */ in ipc_imem_handle_irq()
581 old_phase = ipc_imem->phase; in ipc_imem_handle_irq()
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Diosm_ipc_imem.h265 * respond to any requests. So while introducing new phase
270 * driver call the device power mode D3hot. In this phase
273 * @IPC_P_OFF_REQ: The intermediate phase between cleanup activity starts
275 * @IPC_P_CRASH: The phase indicating CP crash
276 * @IPC_P_CD_READY: The phase indicating CP core dump is ready
280 * @IPC_P_PSI: Primary signed image download phase
282 * @IPC_P_RUN: The phase after flashing to RAM is the RUNTIME phase.
318 * @enter_runtime: 1 means the transition to runtime phase was
326 * @phase: Operating phase like runtime.
368 enum ipc_phase phase; member
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/Linux-v5.15/drivers/clk/meson/
Dclk-phase.c11 #include "clk-phase.h"
40 struct meson_clk_phase_data *phase = meson_clk_phase_data(clk); in meson_clk_phase_get_phase() local
43 val = meson_parm_read(clk->map, &phase->ph); in meson_clk_phase_get_phase()
45 return meson_clk_degrees_from_val(val, phase->ph.width); in meson_clk_phase_get_phase()
51 struct meson_clk_phase_data *phase = meson_clk_phase_data(clk); in meson_clk_phase_set_phase() local
54 val = meson_clk_degrees_to_val(degrees, phase->ph.width); in meson_clk_phase_set_phase()
55 meson_parm_write(clk->map, &phase->ph, val); in meson_clk_phase_set_phase()
68 * The phase of mst_sclk clock output can be controlled independently
72 * If necessary, we can still control the phase in the tdm block
87 /* Get phase 0 and sync it to phase 1 and 2 */ in meson_clk_triphase_sync()
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/Linux-v5.15/drivers/gpu/drm/amd/display/dc/dcn21/
Ddcn21_dccg.c53 int phase; in dccg21_update_dpp_dto() local
57 * program DPP DTO phase and modulo as below in dccg21_update_dpp_dto()
58 * phase = ceiling(dpp_pipe_clk_mhz / 10) in dccg21_update_dpp_dto()
64 * ceiling phase and truncate modulo guarentees the divided in dccg21_update_dpp_dto()
67 phase = (req_dppclk + 9999) / 10000; in dccg21_update_dpp_dto()
69 if (phase > modulo) { in dccg21_update_dpp_dto()
70 /* phase > modulo result in screen corruption in dccg21_update_dpp_dto()
71 * ie phase = 30, mod = 29 for 4k@60 HDMI in dccg21_update_dpp_dto()
74 phase = modulo; in dccg21_update_dpp_dto()
78 * set phase to 10 if dpp isn't used to in dccg21_update_dpp_dto()
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/Linux-v5.15/drivers/gpu/drm/tidss/
Dtidss_dispc_regs.h120 #define DISPC_VID_FIR_COEF_H0(phase) (0x6c + (phase) * 4) argument
122 #define DISPC_VID_FIR_COEF_H0_C(phase) (0x90 + (phase) * 4) argument
125 #define DISPC_VID_FIR_COEF_H12(phase) (0xb4 + (phase) * 4) argument
127 #define DISPC_VID_FIR_COEF_H12_C(phase) (0xf4 + (phase) * 4) argument
130 #define DISPC_VID_FIR_COEF_V0(phase) (0x134 + (phase) * 4) argument
132 #define DISPC_VID_FIR_COEF_V0_C(phase) (0x158 + (phase) * 4) argument
135 #define DISPC_VID_FIR_COEF_V12(phase) (0x17c + (phase) * 4) argument
137 #define DISPC_VID_FIR_COEF_V12_C(phase) (0x1bc + (phase) * 4) argument
/Linux-v5.15/Documentation/devicetree/bindings/mmc/
Dexynos-dw-mshc.txt30 * samsung,dw-mshc-sdr-timing: Specifies the value of CIU clock phase shift value
31 in transmit mode and CIU clock phase shift value in receive mode for single
35 * samsung,dw-mshc-ddr-timing: Specifies the value of CUI clock phase shift value
36 in transmit mode and CIU clock phase shift value in receive mode for double
39 * samsung,dw-mshc-hs400-timing: Specifies the value of CIU TX and RX clock phase
45 - First Cell: CIU clock phase shift value for tx mode.
46 - Second Cell: CIU clock phase shift value for rx mode.
49 - valid value for tx phase shift and rx phase shift is 0 to 7.
50 - when CIU clock divider value is set to 3, all possible 8 phase shift
53 phase shift clocks should be 0.
/Linux-v5.15/drivers/gpu/drm/imx/dcss/
Ddcss-scaler.c178 int phase; in dcss_scaler_gaussian_filter() local
183 for (phase = 0; phase < PSC_STORED_PHASES; phase++) { in dcss_scaler_gaussian_filter()
184 coef[phase][0] = 0; in dcss_scaler_gaussian_filter()
185 coef[phase][PSC_NUM_TAPS - 1] = 0; in dcss_scaler_gaussian_filter()
225 /* override phase 0 with identity filter if specified */ in dcss_scaler_gaussian_filter()
232 for (phase = 0; phase < PSC_STORED_PHASES; phase++) { in dcss_scaler_gaussian_filter()
237 sum += coef[phase][i]; in dcss_scaler_gaussian_filter()
239 ll_temp = coef[phase][i]; in dcss_scaler_gaussian_filter()
243 coef[phase][i] = (int)ll_temp; in dcss_scaler_gaussian_filter()
264 * @use_5_taps: 0 for 7 taps per phase, 1 for 5 taps
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/Linux-v5.15/include/linux/regulator/
Dda9121.h3 * DA9121 Single-channel dual-phase 10A buck converter
4 * DA9130 Single-channel dual-phase 10A buck converter (Automotive)
5 * DA9217 Single-channel dual-phase 6A buck converter
6 * DA9122 Dual-channel single-phase 5A buck converter
7 * DA9131 Dual-channel single-phase 5A buck converter (Automotive)
8 * DA9220 Dual-channel single-phase 3A buck converter
9 * DA9132 Dual-channel single-phase 3A buck converter (Automotive)
/Linux-v5.15/drivers/char/
Dppdev.c20 * SETPHASE set the IEEE 1284 phase of a particular mode. Not to be
37 * GETPHASE gets the current IEEE1284 phase
397 pp->saved_state.phase = info->phase; in pp_do_ioctl()
399 info->phase = pp->state.phase; in pp_do_ioctl()
428 pp->state.phase = init_phase(mode); in pp_do_ioctl()
432 pp->pdev->port->ieee1284.phase = pp->state.phase; in pp_do_ioctl()
452 int phase; in pp_do_ioctl() local
454 if (copy_from_user(&phase, argp, sizeof(phase))) in pp_do_ioctl()
457 /* FIXME: validate phase */ in pp_do_ioctl()
458 pp->state.phase = phase; in pp_do_ioctl()
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/Linux-v5.15/drivers/media/i2c/
Dsaa711x_regs.h112 /* Horizontal phase scaling */
159 /* Horizontal phase scaling */
422 /* Task A: Horizontal phase scaling */
426 "Task A: Horizontal luminance phase offset"},
431 "Task A: Horizontal chrominance phase offset"},
443 "Task A: Vertical chrominance phase offset '00'"},
445 "Task A: Vertical chrominance phase offset '01'"},
447 "Task A: Vertical chrominance phase offset '10'"},
449 "Task A: Vertical chrominance phase offset '11'"},
451 "Task A: Vertical luminance phase offset '00'"},
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/Linux-v5.15/drivers/mmc/core/
Dhost.c215 struct mmc_clk_phase *phase) in mmc_of_parse_timing_phase() argument
221 phase->valid = !rc; in mmc_of_parse_timing_phase()
222 if (phase->valid) { in mmc_of_parse_timing_phase()
223 phase->in_deg = degrees[0]; in mmc_of_parse_timing_phase()
224 phase->out_deg = degrees[1]; in mmc_of_parse_timing_phase()
233 mmc_of_parse_timing_phase(dev, "clk-phase-legacy", in mmc_of_parse_clk_phase()
234 &map->phase[MMC_TIMING_LEGACY]); in mmc_of_parse_clk_phase()
235 mmc_of_parse_timing_phase(dev, "clk-phase-mmc-hs", in mmc_of_parse_clk_phase()
236 &map->phase[MMC_TIMING_MMC_HS]); in mmc_of_parse_clk_phase()
237 mmc_of_parse_timing_phase(dev, "clk-phase-sd-hs", in mmc_of_parse_clk_phase()
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/Linux-v5.15/drivers/staging/iio/Documentation/
Dsysfs-bus-iio-dds36 Stores phase into Y.
38 allows for pin controlled PSK Phase Shift Keying
40 control the desired phase Y which is added to the phase
48 the desired value in rad. If shared across all phase registers
56 Specifies the active phase Y which is added to the phase
68 phase is controlled by the respective phase and frequency
/Linux-v5.15/drivers/scsi/
DNCR5380.c74 * phase goes through the various phases as instructed by the target.
261 {BASR_PHASE_MATCH, "PHASE MATCH"},
340 * NCR5380_print_phase - show SCSI phase
343 * Print the current SCSI phase for debugging purposes
354 shost_printk(KERN_DEBUG, instance, "REQ not asserted, phase unknown.\n"); in NCR5380_print_phase()
359 shost_printk(KERN_DEBUG, instance, "phase %s\n", phases[i].name); in NCR5380_print_phase()
464 * the SCSI bus busy. Check for BUS FREE phase. If not, try to abort the
753 * Called by the interrupt handler when DMA finishes or a phase
767 p = hostdata->connected->SCp.phase; in NCR5380_dma_complete()
791 pr_err("scsi%d: bus stuck in data phase -- probably a single byte overrun!\n", in NCR5380_dma_complete()
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/Linux-v5.15/include/trace/events/
Dclk.h200 TP_PROTO(struct clk_core *core, int phase),
202 TP_ARGS(core, phase),
206 __field( int, phase )
211 __entry->phase = phase;
214 TP_printk("%s %d", __get_str(name), (int)__entry->phase)
219 TP_PROTO(struct clk_core *core, int phase),
221 TP_ARGS(core, phase)
226 TP_PROTO(struct clk_core *core, int phase),
228 TP_ARGS(core, phase)
/Linux-v5.15/drivers/mmc/host/
Ddw_mmc-rockchip.c68 * Set the drive phase offset based on speed mode to achieve hold times. in dw_mci_rk3288_set_ios()
94 int phase; in dw_mci_rk3288_set_ios() local
97 * In almost all cases a 90 degree phase offset will provide in dw_mci_rk3288_set_ios()
102 phase = 90; in dw_mci_rk3288_set_ios()
108 * bus width is 8 we need to double the phase offset in dw_mci_rk3288_set_ios()
112 phase = 180; in dw_mci_rk3288_set_ios()
124 phase = 180; in dw_mci_rk3288_set_ios()
128 clk_set_phase(priv->drv_clk, phase); in dw_mci_rk3288_set_ios()
163 /* Try each phase and extract good ranges */ in dw_mci_rk3288_execute_tuning()
213 dev_info(host->dev, "All phases work, using default phase %d.", in dw_mci_rk3288_execute_tuning()
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/Linux-v5.15/Documentation/devicetree/bindings/mfd/
Daxp20x.txt127 DCDC2 : DC-DC buck : vin2-supply : poly-phase capable
128 DCDC3 : DC-DC buck : vin3-supply : poly-phase capable
130 DCDC5 : DC-DC buck : vin5-supply : poly-phase capable
131 DCDC6 : DC-DC buck : vin6-supply : poly-phase capable
154 DCDCA : DC-DC buck : vina-supply : poly-phase capable
155 DCDCB : DC-DC buck : vinb-supply : poly-phase capable
156 DCDCC : DC-DC buck : vinc-supply : poly-phase capable
157 DCDCD : DC-DC buck : vind-supply : poly-phase capable
158 DCDCE : DC-DC buck : vine-supply : poly-phase capable
171 Additionally, the AXP806 DC-DC regulators support poly-phase arrangements
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/Linux-v5.15/drivers/char/ipmi/
Dkcs_bmc_cdev_ipmi.c76 enum kcs_ipmi_phases phase; member
133 priv->phase = KCS_PHASE_ERROR; in kcs_bmc_ipmi_force_abort()
145 switch (priv->phase) { in kcs_bmc_ipmi_handle_data()
147 priv->phase = KCS_PHASE_WRITE_DATA; in kcs_bmc_ipmi_handle_data()
165 priv->phase = KCS_PHASE_WRITE_DONE; in kcs_bmc_ipmi_handle_data()
187 priv->phase = KCS_PHASE_IDLE; in kcs_bmc_ipmi_handle_data()
198 priv->phase = KCS_PHASE_ABORT_ERROR2; in kcs_bmc_ipmi_handle_data()
205 priv->phase = KCS_PHASE_IDLE; in kcs_bmc_ipmi_handle_data()
224 priv->phase = KCS_PHASE_WRITE_START; in kcs_bmc_ipmi_handle_cmd()
231 if (priv->phase != KCS_PHASE_WRITE_DATA) { in kcs_bmc_ipmi_handle_cmd()
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