per\-core (full) in projects: Linux-v6.1

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/Linux-v6.1/tools/perf/pmu-events/arch/x86/broadwellde/
D	uncore-power.json	11 "BriefDescription": "Core C State Transition Cycles", 16 …Description": "Number of cycles spent performing core C state transitions. There is one event per… 20 "BriefDescription": "Core C State Transition Cycles", 25 …Description": "Number of cycles spent performing core C state transitions. There is one event per… 29 "BriefDescription": "Core C State Transition Cycles", 34 …Description": "Number of cycles spent performing core C state transitions. There is one event per… 38 "BriefDescription": "Core C State Transition Cycles", 43 …Description": "Number of cycles spent performing core C state transitions. There is one event per… 47 "BriefDescription": "Core C State Transition Cycles", 52 …Description": "Number of cycles spent performing core C state transitions. There is one event per… [all …]
D	bdwde-metrics.json	4 "MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / SLOTS", 7 …core responsible to fetch operations that are executed later on by the Backend part. Within the Fr… 12 "MetricExpr": "4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / SLOTS", 15 …he CPU was stalled due to Frontend latency issues. For example; instruction-cache misses; iTLB mi… 39 … corrected path; following all sorts of miss-predicted branches. For example; branchy code with lo… 60 "MetricExpr": "tma_branch_resteers - tma_mispredicts_resteers - tma_clears_resteers", 71 …o switches from DSB to MITE pipelines. The DSB (decoded i-cache) is a Uop Cache where the front-en… 87 … Commonly used instructions are optimized for delivery by the DSB (decoded i-cache) or MITE (legac… 92 "MetricExpr": "tma_frontend_bound - tma_fetch_latency", 99 …"BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limite… [all …]
/Linux-v6.1/tools/perf/pmu-events/arch/powerpc/power8/
D	metrics.json	21 "BriefDescription": "% of Branch miss predictions per instruction", 27 "BriefDescription": "Count cache branch misprediction per instruction", 39 "BriefDescription": "CR MisPredictions per Instruction", 46 "MetricExpr": "(PM_BR_MPRED_TA - PM_BR_MPRED_CCACHE) / PM_RUN_INST_CMPL * 100", 52 …"MetricExpr": "(PM_BR_MPRED_TA - PM_BR_MPRED_CCACHE) / (PM_BR_PRED_LSTACK_BR0 + PM_BR_PRED_LSTACK_… 57 "BriefDescription": "TA MisPredictions per Instruction", 124 "MetricExpr": "(PM_CMPLU_STALL_BRU_CRU - PM_CMPLU_STALL_BRU) / PM_RUN_INST_CMPL", 135 "BriefDescription": "Cycles stalled by FXU Multi-Cycle Instructions", 148 …"MetricExpr": "(PM_CMPLU_STALL_FXU / PM_RUN_INST_CMPL) - (PM_CMPLU_STALL_FXLONG / PM_RUN_INST_CMPL… 208 "MetricExpr": "(PM_GCT_NOSLOT_IC_MISS - PM_GCT_NOSLOT_IC_L3MISS) / PM_RUN_INST_CMPL", [all …]
/Linux-v6.1/tools/perf/pmu-events/arch/x86/haswell/
D	hsw-metrics.json	4 "MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / SLOTS", 7 …core responsible to fetch operations that are executed later on by the Backend part. Within the Fr… 12 …Expr": "4 * min(CPU_CLK_UNHALTED.THREAD, IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE) / SLOTS", 15 …he CPU was stalled due to Frontend latency issues. For example; instruction-cache misses; iTLB mi… 38 … corrected path; following all sorts of miss-predicted branches. For example; branchy code with lo… 46 …o switches from DSB to MITE pipelines. The DSB (decoded i-cache) is a Uop Cache where the front-en… 62 … Commonly used instructions are optimized for delivery by the DSB (decoded i-cache) or MITE (legac… 67 "MetricExpr": "tma_frontend_bound - tma_fetch_latency", 74 …"BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limite… 75 "MetricExpr": "(IDQ.ALL_MITE_CYCLES_ANY_UOPS - IDQ.ALL_MITE_CYCLES_4_UOPS) / CORE_CLKS / 2", [all …]
/Linux-v6.1/tools/perf/pmu-events/arch/x86/ivybridge/
D	ivb-metrics.json	4 "MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / SLOTS", 7 …core responsible to fetch operations that are executed later on by the Backend part. Within the Fr… 12 …Expr": "4 * min(CPU_CLK_UNHALTED.THREAD, IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE) / SLOTS", 15 …he CPU was stalled due to Frontend latency issues. For example; instruction-cache misses; iTLB mi… 20 "MetricExpr": "ICACHE.IFETCH_STALL / CLKS - tma_itlb_misses", 38 … corrected path; following all sorts of miss-predicted branches. For example; branchy code with lo… 46 …o switches from DSB to MITE pipelines. The DSB (decoded i-cache) is a Uop Cache where the front-en… 62 … Commonly used instructions are optimized for delivery by the DSB (decoded i-cache) or MITE (legac… 67 "MetricExpr": "tma_frontend_bound - tma_fetch_latency", 74 …"BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limite… [all …]
/Linux-v6.1/tools/perf/pmu-events/arch/x86/broadwell/
D	bdw-metrics.json	4 "MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / SLOTS", 7 …core responsible to fetch operations that are executed later on by the Backend part. Within the Fr… 12 "MetricExpr": "4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / SLOTS", 15 …he CPU was stalled due to Frontend latency issues. For example; instruction-cache misses; iTLB mi… 38 … corrected path; following all sorts of miss-predicted branches. For example; branchy code with lo… 57 "MetricExpr": "tma_branch_resteers - tma_mispredicts_resteers - tma_clears_resteers", 68 …o switches from DSB to MITE pipelines. The DSB (decoded i-cache) is a Uop Cache where the front-en… 84 … Commonly used instructions are optimized for delivery by the DSB (decoded i-cache) or MITE (legac… 89 "MetricExpr": "tma_frontend_bound - tma_fetch_latency", 96 …"BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limite… [all …]
/Linux-v6.1/tools/perf/pmu-events/arch/x86/ivytown/
D	ivt-metrics.json	4 "MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / SLOTS", 7 …core responsible to fetch operations that are executed later on by the Backend part. Within the Fr… 12 …Expr": "4 * min(CPU_CLK_UNHALTED.THREAD, IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE) / SLOTS", 15 …he CPU was stalled due to Frontend latency issues. For example; instruction-cache misses; iTLB mi… 20 "MetricExpr": "ICACHE.IFETCH_STALL / CLKS - tma_itlb_misses", 38 … corrected path; following all sorts of miss-predicted branches. For example; branchy code with lo… 46 …o switches from DSB to MITE pipelines. The DSB (decoded i-cache) is a Uop Cache where the front-en… 62 … Commonly used instructions are optimized for delivery by the DSB (decoded i-cache) or MITE (legac… 67 "MetricExpr": "tma_frontend_bound - tma_fetch_latency", 74 …"BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limite… [all …]
D	uncore-power.json	11 "BriefDescription": "Core 0 C State Transition Cycles", 16 …Description": "Number of cycles spent performing core C state transitions. There is one event per… 20 "BriefDescription": "Core 10 C State Transition Cycles", 25 …Description": "Number of cycles spent performing core C state transitions. There is one event per… 29 "BriefDescription": "Core 11 C State Transition Cycles", 34 …Description": "Number of cycles spent performing core C state transitions. There is one event per… 38 "BriefDescription": "Core 12 C State Transition Cycles", 43 …Description": "Number of cycles spent performing core C state transitions. There is one event per… 47 "BriefDescription": "Core 13 C State Transition Cycles", 52 …Description": "Number of cycles spent performing core C state transitions. There is one event per… [all …]
/Linux-v6.1/tools/perf/pmu-events/arch/powerpc/power9/
D	metrics.json	8 "BriefDescription": "Count cache branch misprediction per instruction", 56 …"BriefDescription": "Finish stall because the NTF instruction was a multi-cycle instruction issued… 63 "MetricExpr": "dfu_stall_cpi - dflong_stall_cpi", 75 "MetricExpr": "dmiss_non_local_stall_cpi - dmiss_remote_stall_cpi", 93 "MetricExpr": "dmiss_l2l3_stall_cpi - dmiss_l2l3_conflict_stall_cpi", 117 "MetricExpr": "dmiss_l3miss_stall_cpi - dmiss_l21_l31_stall_cpi - dmiss_lmem_stall_cpi", 129 "MetricExpr": "dp_stall_cpi - dplong_stall_cpi", 140 …"BriefDescription": "Finish stall because the NTF instruction was a scalar multi-cycle instruction… 176 "MetricExpr": "exec_unit_stall_cpi - scalar_stall_cpi - vector_stall_cpi", 187 …ction is not allowed to complete because any of the 4 threads in the same core suffered a flush, w… [all …]
/Linux-v6.1/tools/perf/pmu-events/arch/x86/tigerlake/
D	tgl-metrics.json	4 …"MetricExpr": "topdown\\-fe\\-bound / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-ret… 7 …core responsible to fetch operations that are executed later on by the Backend part. Within the Fr… 12 …"MetricExpr": "(5 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE - INT_MISC.UOP_DROPPING) / SLO… 15 …he CPU was stalled due to Frontend latency issues. For example; instruction-cache misses; iTLB mi… 39 … corrected path; following all sorts of miss-predicted branches. For example; branchy code with lo… 52 …"MetricExpr": "(1 - (BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS… 71 …o switches from DSB to MITE pipelines. The DSB (decoded i-cache) is a Uop Cache where the front-en… 87 … Commonly used instructions are optimized for delivery by the DSB (decoded i-cache) or MITE (legac… 92 "MetricExpr": "max(0, tma_frontend_bound - tma_fetch_latency)", 99 …"BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limite… [all …]
/Linux-v6.1/tools/perf/pmu-events/arch/x86/icelake/
D	icl-metrics.json	4 …"MetricExpr": "topdown\\-fe\\-bound / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-ret… 7 …core responsible to fetch operations that are executed later on by the Backend part. Within the Fr… 12 …"MetricExpr": "(5 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE - INT_MISC.UOP_DROPPING) / SLO… 15 …he CPU was stalled due to Frontend latency issues. For example; instruction-cache misses; iTLB mi… 39 … corrected path; following all sorts of miss-predicted branches. For example; branchy code with lo… 52 …"MetricExpr": "(1 - (BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS… 71 …o switches from DSB to MITE pipelines. The DSB (decoded i-cache) is a Uop Cache where the front-en… 87 … Commonly used instructions are optimized for delivery by the DSB (decoded i-cache) or MITE (legac… 92 "MetricExpr": "max(0, tma_frontend_bound - tma_fetch_latency)", 99 …"BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limite… [all …]
/Linux-v6.1/tools/perf/pmu-events/arch/x86/broadwellx/
D	bdx-metrics.json	4 "MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / SLOTS", 7 …core responsible to fetch operations that are executed later on by the Backend part. Within the Fr… 12 "MetricExpr": "4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / SLOTS", 15 …he CPU was stalled due to Frontend latency issues. For example; instruction-cache misses; iTLB mi… 38 … corrected path; following all sorts of miss-predicted branches. For example; branchy code with lo… 57 "MetricExpr": "tma_branch_resteers - tma_mispredicts_resteers - tma_clears_resteers", 68 …o switches from DSB to MITE pipelines. The DSB (decoded i-cache) is a Uop Cache where the front-en… 84 … Commonly used instructions are optimized for delivery by the DSB (decoded i-cache) or MITE (legac… 89 "MetricExpr": "tma_frontend_bound - tma_fetch_latency", 96 …"BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limite… [all …]
/Linux-v6.1/tools/perf/pmu-events/arch/x86/skylake/
D	skl-metrics.json	4 "MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / SLOTS", 7 …core responsible to fetch operations that are executed later on by the Backend part. Within the Fr… 12 "MetricExpr": "4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / SLOTS", 15 …he CPU was stalled due to Frontend latency issues. For example; instruction-cache misses; iTLB mi… 39 … corrected path; following all sorts of miss-predicted branches. For example; branchy code with lo… 52 …"MetricExpr": "(1 - (BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS… 71 …o switches from DSB to MITE pipelines. The DSB (decoded i-cache) is a Uop Cache where the front-en… 87 … Commonly used instructions are optimized for delivery by the DSB (decoded i-cache) or MITE (legac… 92 "MetricExpr": "tma_frontend_bound - tma_fetch_latency", 99 …"BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limite… [all …]
/Linux-v6.1/tools/perf/tests/shell/
D	stat+csv_output.sh	`3 # SPDX-License-Identifier: (LGPL-2.1 OR BSD-2-Clause) 7 set -e 13 local -i cnt=0 17 in "--no-args") exp=6 18 ;; "--system-wide") exp=6 19 ;; "--event") exp=6 20 ;; "--interval") exp=7 21 ;; "--per-thread") exp=7 22 ;; "--system-wide-no-aggr") exp=7 23 [ $(uname -m) = "s390x" ] && exp='^[6-7]$' [all …]`
D	stat+json_output.sh	3 # SPDX-License-Identifier: (LGPL-2.1 OR BSD-2-Clause) 7 set -e 29 [ $(id -u) != 0 ] && [ $(cat /proc/sys/kernel/perf_event_paranoid) -gt $1 ] 34 echo -n "Checking json output: no args " 35 perf stat -j true 2>&1 \| $PYTHON $pythonchecker --no-args 41 echo -n "Checking json output: system wide " 47 perf stat -j -a true 2>&1 \| $PYTHON $pythonchecker --system-wide 53 echo -n "Checking json output: system wide " 59 echo -n "Checking json output: system wide no aggregation " 60 perf stat -j -A -a --no-merge true 2>&1 \| $PYTHON $pythonchecker --system-wide-no-aggr [all …]
/Linux-v6.1/tools/perf/Documentation/
D	perf-stat.txt	`1 perf-stat(1) 5 ---- 6 perf-stat - Run a command and gather performance counter statistics 9 -------- 11 'perf stat' [-e <EVENT> \| --event=EVENT] [-a] <command> 12 'perf stat' [-e <EVENT> \| --event=EVENT] [-a] \-- <command> [<options>] 13 'perf stat' [-e <EVENT> \| --event=EVENT] [-a] record [-o file] \-- <command> [<options>] 14 'perf stat' report [-i file] 17 ----------- 23 ------- [all …]`
/Linux-v6.1/Documentation/x86/
D	topology.rst	`1 .. SPDX-License-Identifier: GPL-2.0 11 The architecture-agnostic topology definitions are in 12 Documentation/admin-guide/cputopology.rst. This file holds x86-specific 17 Needless to say, code should use the generic functions - this file is only 35 - packages 36 - cores 37 - threads 48 Package-related topology information in the kernel: 50 - cpuinfo_x86.x86_max_cores: 54 - cpuinfo_x86.x86_max_dies: [all …]`
/Linux-v6.1/tools/perf/pmu-events/arch/x86/haswellx/
D	hsx-metrics.json	4 "MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / SLOTS", 7 …core responsible to fetch operations that are executed later on by the Backend part. Within the Fr… 12 …Expr": "4 * min(CPU_CLK_UNHALTED.THREAD, IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE) / SLOTS", 15 …he CPU was stalled due to Frontend latency issues. For example; instruction-cache misses; iTLB mi… 38 … corrected path; following all sorts of miss-predicted branches. For example; branchy code with lo… 46 …o switches from DSB to MITE pipelines. The DSB (decoded i-cache) is a Uop Cache where the front-en… 62 … Commonly used instructions are optimized for delivery by the DSB (decoded i-cache) or MITE (legac… 67 "MetricExpr": "tma_frontend_bound - tma_fetch_latency", 74 …"BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limite… 75 "MetricExpr": "(IDQ.ALL_MITE_CYCLES_ANY_UOPS - IDQ.ALL_MITE_CYCLES_4_UOPS) / CORE_CLKS / 2", [all …]
/Linux-v6.1/tools/perf/pmu-events/arch/arm64/arm/cortex-a55/
D	cache.json	105 …unted, regardless of whether they allocate. If either the core is configured without a per-core L2… 108 …unted, regardless of whether they allocate. If either the core is configured without a per-core L2… 111 …core is configured with a per-core L2 cache: This event does not count. +//0 If the core is config… 114 …core is configured with a per-core L2 cache: This event does not count. +//0 If the core is config… 117 …This event counts any linefills from the prefetcher which cause an allocation into the L1 D-cache", 120 … This event counts any linefills from the prefetcher which cause an allocation into the L1 D-cache" 123 …he write streaming mode. This event counts for each cycle where the core is in write-streaming mod… 126 …he write streaming mode. This event counts for each cycle where the core is in write-streaming mod… 129 …ta cache entering write streaming mode.This event counts for each entry into write-streaming mode", 132 …ata cache entering write streaming mode.This event counts for each entry into write-streaming mode" [all …]
/Linux-v6.1/tools/perf/pmu-events/arch/x86/cascadelakex/
D	clx-metrics.json	4 "MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / SLOTS", 7 …core responsible to fetch operations that are executed later on by the Backend part. Within the Fr… 12 "MetricExpr": "4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / SLOTS", 15 …he CPU was stalled due to Frontend latency issues. For example; instruction-cache misses; iTLB mi… 39 … corrected path; following all sorts of miss-predicted branches. For example; branchy code with lo… 52 …"MetricExpr": "(1 - (BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS… 71 …o switches from DSB to MITE pipelines. The DSB (decoded i-cache) is a Uop Cache where the front-en… 87 … Commonly used instructions are optimized for delivery by the DSB (decoded i-cache) or MITE (legac… 92 "MetricExpr": "tma_frontend_bound - tma_fetch_latency", 99 …"BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limite… [all …]
/Linux-v6.1/tools/perf/pmu-events/arch/x86/skylakex/
D	skx-metrics.json	4 "MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / SLOTS", 7 …core responsible to fetch operations that are executed later on by the Backend part. Within the Fr… 12 "MetricExpr": "4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / SLOTS", 15 …he CPU was stalled due to Frontend latency issues. For example; instruction-cache misses; iTLB mi… 39 … corrected path; following all sorts of miss-predicted branches. For example; branchy code with lo… 52 …"MetricExpr": "(1 - (BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS… 71 …o switches from DSB to MITE pipelines. The DSB (decoded i-cache) is a Uop Cache where the front-en… 87 … Commonly used instructions are optimized for delivery by the DSB (decoded i-cache) or MITE (legac… 92 "MetricExpr": "tma_frontend_bound - tma_fetch_latency", 99 …"BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limite… [all …]
/Linux-v6.1/tools/perf/pmu-events/arch/x86/jaketown/
D	jkt-metrics.json	4 "MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / SLOTS", 7 …core responsible to fetch operations that are executed later on by the Backend part. Within the Fr… 12 …Expr": "4 * min(CPU_CLK_UNHALTED.THREAD, IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE) / SLOTS", 15 …he CPU was stalled due to Frontend latency issues. For example; instruction-cache misses; iTLB mi… 31 … corrected path; following all sorts of miss-predicted branches. For example; branchy code with lo… 39 …o switches from DSB to MITE pipelines. The DSB (decoded i-cache) is a Uop Cache where the front-en… 55 … Commonly used instructions are optimized for delivery by the DSB (decoded i-cache) or MITE (legac… 60 "MetricExpr": "tma_frontend_bound - tma_fetch_latency", 68 …"MetricExpr": "(UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * ((INT_MISC.RECOVERY_CYCLES_ANY /… 71 …s for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For… [all …]
/Linux-v6.1/tools/perf/pmu-events/arch/x86/sandybridge/
D	snb-metrics.json	4 "MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / SLOTS", 7 …core responsible to fetch operations that are executed later on by the Backend part. Within the Fr… 12 …Expr": "4 * min(CPU_CLK_UNHALTED.THREAD, IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE) / SLOTS", 15 …he CPU was stalled due to Frontend latency issues. For example; instruction-cache misses; iTLB mi… 31 … corrected path; following all sorts of miss-predicted branches. For example; branchy code with lo… 39 …o switches from DSB to MITE pipelines. The DSB (decoded i-cache) is a Uop Cache where the front-en… 55 … Commonly used instructions are optimized for delivery by the DSB (decoded i-cache) or MITE (legac… 60 "MetricExpr": "tma_frontend_bound - tma_fetch_latency", 68 …"MetricExpr": "(UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * ((INT_MISC.RECOVERY_CYCLES_ANY /… 71 …s for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For… [all …]
/Linux-v6.1/tools/perf/pmu-events/arch/x86/icelakex/
D	icx-metrics.json	4 …"MetricExpr": "topdown\\-fe\\-bound / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-ret… 7 …core responsible to fetch operations that are executed later on by the Backend part. Within the Fr… 12 …"MetricExpr": "(5 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE - INT_MISC.UOP_DROPPING) / SLO… 15 …he CPU was stalled due to Frontend latency issues. For example; instruction-cache misses; iTLB mi… 39 … corrected path; following all sorts of miss-predicted branches. For example; branchy code with lo… 52 …"MetricExpr": "(1 - (BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS… 71 …o switches from DSB to MITE pipelines. The DSB (decoded i-cache) is a Uop Cache where the front-en… 87 … Commonly used instructions are optimized for delivery by the DSB (decoded i-cache) or MITE (legac… 92 "MetricExpr": "max(0, tma_frontend_bound - tma_fetch_latency)", 99 …"BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limite… [all …]
/Linux-v6.1/tools/perf/pmu-events/arch/x86/alderlake/
D	adl-metrics.json	4 …"MetricExpr": "topdown\\-fe\\-bound / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-ret… 7 …core responsible to fetch operations that are executed later on by the Backend part. Within the Fr… 13 …etricExpr": "(topdown\\-fetch\\-lat / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-ret… 16 …he CPU was stalled due to Frontend latency issues. For example; instruction-cache misses; iTLB mi… 43 … corrected path; following all sorts of miss-predicted branches. For example; branchy code with lo… 58 …"MetricExpr": "(1 - (tma_branch_mispredicts / tma_bad_speculation)) * INT_MISC.CLEAR_RESTEER_CYCLE… 79 …o switches from DSB to MITE pipelines. The DSB (decoded i-cache) is a Uop Cache where the front-en… 97 … Commonly used instructions are optimized for delivery by the DSB (decoded i-cache) or MITE (legac… 103 "MetricExpr": "max(0, tma_frontend_bound - tma_fetch_latency)", 111 …"BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limite… [all …]

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