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/Linux-v5.4/drivers/scsi/mpt3sas/
Dmpt3sas_transport.c5 * Copyright (C) 2012-2014 LSI Corporation
6 * Copyright (C) 2013-2014 Avago Technologies
7 * (mailto: MPT-FusionLinux.pdl@avagotech.com)
22 * LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT,
41 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301,
64 * _transport_sas_node_find_by_sas_address - sas node search
65 * @ioc: per adapter object
67 * Context: Calling function should acquire ioc->sas_node_lock.
76 if (ioc->sas_hba.sas_address == sas_address) in _transport_sas_node_find_by_sas_address()
77 return &ioc->sas_hba; in _transport_sas_node_find_by_sas_address()
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/Linux-v5.4/include/uapi/linux/
Datmioc.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
2 /* atmioc.h - ranges for ATM-related ioctl numbers */
4 /* Written 1995-1999 by Werner Almesberger, EPFL LRC/ICA */
8 * See http://icawww1.epfl.ch/linux-atm/magic.html for the complete list of
19 #define ATMIOC_PHYCOM 0x00 /* PHY device common ioctls, globally unique */
21 #define ATMIOC_PHYTYP 0x10 /* PHY dev type ioctls, unique per PHY type */
23 #define ATMIOC_PHYPRV 0x30 /* PHY dev private ioctls, unique per driver */
27 #define ATMIOC_SARPRV 0x60 /* SAR dev private ioctls, unique per driver */
31 #define ATMIOC_BACKEND 0x90 /* ATM generic backend ioctls, u. per backend */
33 /* 0xb0-0xbf: Reserved for future use */
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/Linux-v5.4/Documentation/devicetree/bindings/net/
Dmdio.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andrew Lunn <andrew@lunn.ch>
11 - Florian Fainelli <f.fainelli@gmail.com>
12 - Heiner Kallweit <hkallweit1@gmail.com>
16 MDIO bus must have a list of child nodes, one per device on the
17 bus. These should follow the generic ethernet-phy.yaml document, or
24 "#address-cells":
27 "#size-cells":
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Dmarvell-pp2.txt6 - compatible: should be one of:
7 "marvell,armada-375-pp2"
8 "marvell,armada-7k-pp2"
9 - reg: addresses and length of the register sets for the device.
10 For "marvell,armada-375-pp2", must contain the following register
12 - common controller registers
13 - LMS registers
14 - one register area per Ethernet port
15 For "marvell,armada-7k-pp2", must contain the following register
17 - packet processor registers
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/Linux-v5.4/Documentation/devicetree/bindings/ufs/
Dufshcd-pltfrm.txt3 UFSHC nodes are defined to describe on-chip UFS host controllers.
7 - compatible : must contain "jedec,ufs-1.1" or "jedec,ufs-2.0"
10 SoC-specific compatible along with "qcom,ufshc" and
12 "qcom,msm8994-ufshc", "qcom,ufshc", "jedec,ufs-2.0"
13 "qcom,msm8996-ufshc", "qcom,ufshc", "jedec,ufs-2.0"
14 "qcom,msm8998-ufshc", "qcom,ufshc", "jedec,ufs-2.0"
15 "qcom,sdm845-ufshc", "qcom,ufshc", "jedec,ufs-2.0"
16 - interrupts : <interrupt mapping for UFS host controller IRQ>
17 - reg : <registers mapping>
20 - phys : phandle to UFS PHY node
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/Linux-v5.4/Documentation/networking/dsa/
Ddsa.rst22 An Ethernet switch is typically comprised of multiple front-panel ports, and one
27 gateways, or even top-of-the rack switches. This host Ethernet controller will
36 For each front-panel port, DSA will create specialized network devices which are
37 used as controlling and data-flowing endpoints for use by the Linux networking
46 - what port is this frame coming from
47 - what was the reason why this frame got forwarded
48 - how to send CPU originated traffic to specific ports
52 on Port-based VLAN IDs).
57 - the "cpu" port is the Ethernet switch facing side of the management
61 - the "dsa" port(s) are just conduits between two or more switches, and as such
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/Linux-v5.4/Documentation/devicetree/bindings/pci/
Drockchip-pcie-host.txt4 - #address-cells: Address representation for root ports, set to <3>
5 - #size-cells: Size representation for root ports, set to <2>
6 - #interrupt-cells: specifies the number of cells needed to encode an
8 - compatible: Should contain "rockchip,rk3399-pcie"
9 - reg: Two register ranges as listed in the reg-names property
10 - reg-names: Must include the following names
11 - "axi-base"
12 - "apb-base"
13 - clocks: Must contain an entry for each entry in clock-names.
14 See ../clocks/clock-bindings.txt for details.
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Dcdns,cdns-pcie-ep.txt4 - compatible: Should contain "cdns,cdns-pcie-ep" to identify the IP used.
5 - reg: Should contain the controller register base address and AXI interface
7 - reg-names: Must be "reg" and "mem" respectively.
8 - cdns,max-outbound-regions: Set to maximum number of outbound regions
11 - max-functions: Maximum number of functions that can be configured (default 1).
12 - phys: From PHY bindings: List of Generic PHY phandles. One per lane if more
13 than one in the list. If only one PHY listed it must manage all lanes.
14 - phy-names: List of names to identify the PHY.
19 compatible = "cdns,cdns-pcie-ep";
22 reg-names = "reg", "mem";
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Dspear13xx-pcie.txt4 SPEAr13XX uses the Synopsys DesignWare PCIe controller and ST MiPHY as PHY
8 - compatible : should be "st,spear1340-pcie", "snps,dw-pcie".
9 - phys : phandle to PHY node associated with PCIe controller
10 - phy-names : must be "pcie-phy"
11 - All other definitions as per generic PCI bindings
14 - st,pcie-is-gen1 indicates that forced gen1 initialization is needed.
/Linux-v5.4/drivers/net/wireless/intel/iwlwifi/fw/api/
Dbinding.h8 * Copyright(c) 2012 - 2014 Intel Corporation. All rights reserved.
9 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
10 * Copyright(c) 2016 - 2017 Intel Deutschland GmbH
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
30 * Copyright(c) 2012 - 2014 Intel Corporation. All rights reserved.
31 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
32 * Copyright(c) 2016 - 2017 Intel Deutschland GmbH
70 * struct iwl_binding_cmd_v1 - configuring bindings
77 * @phy: PHY id and color which belongs to the binding,
86 __le32 phy; member
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/Linux-v5.4/Documentation/devicetree/bindings/phy/
Drockchip-pcie-phy.txt1 Rockchip PCIE PHY
2 -----------------------
5 - compatible: rockchip,rk3399-pcie-phy
6 - clocks: Must contain an entry in clock-names.
7 See ../clocks/clock-bindings.txt for details.
8 - clock-names: Must be "refclk"
9 - resets: Must contain an entry in reset-names.
11 - reset-names: Must be "phy"
13 Required properties for legacy PHY mode (deprecated):
14 - #phy-cells: must be 0
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Dnvidia,tegra124-xusb-padctl.txt11 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
12 super-speed USB. Other lanes are for various types of low-speed, full-speed
13 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
14 contains a software-configurable mux that sits between the I/O controller
17 In addition to per-lane configuration, USB 3.0 ports may require additional
18 settings on a per-board basis.
20 Pads will be represented as children of the top-level XUSB pad controller
23 PHY bindings, as described by the phy-bindings.txt file in this directory.
29 abstraction of the signals that are routed to a USB receptacle (i.e. a PHY
34 --------------------
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Dphy-stm32-usbphyc.txt1 STMicroelectronics STM32 USB HS PHY controller
3 The STM32 USBPHYC block contains a dual port High Speed UTMI+ PHY and a UTMI
4 switch. It controls PHY configuration and status, and the UTMI+ switch that
5 selects either OTG or HOST controller for the second PHY port. It also sets
11 |_ PHY port#1 _________________ HOST controller
14 |_ PHY port#2 ----| |________________
19 Phy provider node
23 - compatible: must be "st,stm32mp1-usbphyc"
24 - reg: address and length of the usb phy control register set
25 - clocks: phandle + clock specifier for the PLL phy clock
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/Linux-v5.4/Documentation/devicetree/bindings/memory-controllers/ti/
Demif.txt3 EMIF - External Memory Interface - is an SDRAM controller used in
11 - compatible : Should be of the form "ti,emif-<ip-rev>" where <ip-rev>
14 "ti,emif-am3352"
15 "ti,emif-am4372"
16 "ti,emif-dra7xx"
17 "ti,emif-keystone"
19 - phy-type : <u32> indicating the DDR phy type. Following are the
21 <1> : Attila PHY
22 <2> : Intelli PHY
24 - device-handle : phandle to a "lpddr2" node representing the memory part
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/Linux-v5.4/drivers/staging/media/omap4iss/
Diss_csiphy.c1 // SPDX-License-Identifier: GPL-2.0+
3 * TI OMAP4 ISS V4L2 Driver - CSI PHY module
14 #include "../../../../arch/arm/mach-omap2/control.h"
21 * csiphy_lanes_config - Configuration of CSIPHY lanes.
24 * Called with phy->mutex taken.
26 static void csiphy_lanes_config(struct iss_csiphy *phy) in csiphy_lanes_config() argument
31 reg = iss_reg_read(phy->iss, phy->cfg_regs, CSI2_COMPLEXIO_CFG); in csiphy_lanes_config()
33 for (i = 0; i < phy->max_data_lanes; i++) { in csiphy_lanes_config()
36 reg |= (phy->lanes.data[i].pol ? in csiphy_lanes_config()
38 reg |= (phy->lanes.data[i].pos << in csiphy_lanes_config()
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/Linux-v5.4/Documentation/devicetree/bindings/media/
Dcdns,csi2rx.txt1 Cadence MIPI-CSI2 RX controller
4 The Cadence MIPI-CSI2 RX controller is a CSI-2 bridge supporting up to 4 CSI
8 - compatible: must be set to "cdns,csi2rx" and an SoC-specific compatible
9 - reg: base address and size of the memory mapped region
10 - clocks: phandles to the clocks driving the controller
11 - clock-names: must contain:
14 * pixel_if[0-3]_clk: pixel stream output clock, one for each stream
18 - phys: phandle to the external D-PHY, phy-names must be provided
19 - phy-names: must contain "dphy", if the implementation uses an
20 external D-PHY
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Dcdns,csi2tx.txt1 Cadence MIPI-CSI2 TX controller
4 The Cadence MIPI-CSI2 TX controller is a CSI-2 bridge supporting up to
8 - compatible: must be set to "cdns,csi2tx" or "cdns,csi2tx-1.3"
9 for version 1.3 of the controller, "cdns,csi2tx-2.1" for v2.1
10 - reg: base address and size of the memory mapped region
11 - clocks: phandles to the clocks driving the controller
12 - clock-names: must contain:
15 * pixel_if[0-3]_clk: pixel stream output clock, one for each stream
19 - phys: phandle to the D-PHY. If it is set, phy-names need to be set
20 - phy-names: must contain "dphy"
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/Linux-v5.4/drivers/net/wireless/broadcom/brcm80211/brcmsmac/
Dmain.h48 * Usage example, e.g. a three-bit field (bits 4-6):
52 * regval = R_REG(osh, &regs->regfoo);
55 * W_REG(osh, &regs->regfoo, regval);
58 (((unsigned)1 << (width)) - 1)
67 /* max # supported core revisions (0 .. MAXCOREREV - 1) */
76 #define BRCMS_SHORTSLOT_AUTO -1 /* Driver will manage Shortslot setting */
91 #define TXFID_QUEUE_MASK 0x0007 /* Bits 0-2 */
92 #define TXFID_SEQ_MASK 0x7FE0 /* Bits 5-15 */
145 ((uint)((wlc)->band->bandunit ? BAND_2G_INDEX : BAND_5G_INDEX))
152 * gmode_user: user config gmode, operating band->gmode is different.
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/Linux-v5.4/Documentation/devicetree/bindings/usb/
Dusb-nop-xceiv.txt1 USB NOP PHY
4 - compatible: should be usb-nop-xceiv
5 - #phy-cells: Must be 0
8 - clocks: phandle to the PHY clock. Use as per Documentation/devicetree
9 /bindings/clock/clock-bindings.txt
10 This property is required if clock-frequency is specified.
12 - clock-names: Should be "main_clk"
14 - clock-frequency: the clock frequency (in Hz) that the PHY clock must
17 - vcc-supply: phandle to the regulator that provides power to the PHY.
19 - reset-gpios: Should specify the GPIO for reset.
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/Linux-v5.4/arch/arm64/boot/dts/freescale/
Dimx8mq.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
4 * Copyright (C) 2017-2018 Pengutronix, Lucas Stach <kernel@pengutronix.de>
7 #include <dt-bindings/clock/imx8mq-clock.h>
8 #include <dt-bindings/power/imx8mq-power.h>
9 #include <dt-bindings/reset/imx8mq-reset.h>
10 #include <dt-bindings/gpio/gpio.h>
11 #include "dt-bindings/input/input.h"
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/thermal/thermal.h>
14 #include "imx8mq-pinfunc.h"
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/Linux-v5.4/arch/arm/boot/dts/
Dsunxi-h3-h5.dtsi4 * This file is dual-licensed: you can use it either under the terms
43 #include <dt-bindings/clock/sun8i-de2.h>
44 #include <dt-bindings/clock/sun8i-h3-ccu.h>
45 #include <dt-bindings/clock/sun8i-r-ccu.h>
46 #include <dt-bindings/interrupt-controller/arm-gic.h>
47 #include <dt-bindings/reset/sun8i-de2.h>
48 #include <dt-bindings/reset/sun8i-h3-ccu.h>
49 #include <dt-bindings/reset/sun8i-r-ccu.h>
52 interrupt-parent = <&gic>;
53 #address-cells = <1>;
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Dimx35.dtsi1 // SPDX-License-Identifier: GPL-2.0
7 #include "imx35-pinfunc.h"
10 #address-cells = <1>;
11 #size-cells = <1>;
14 * pre-existing /chosen node to be available to insert the
38 #address-cells = <1>;
39 #size-cells = <0>;
42 compatible = "arm,arm1136jf-s";
48 avic: avic-interrupt-controller@68000000 {
49 compatible = "fsl,imx35-avic", "fsl,avic";
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/Linux-v5.4/drivers/net/wireless/broadcom/b43legacy/
Dxmit.h1 /* SPDX-License-Identifier: GPL-2.0 */
29 __le16 phy_ctl; /* PHY TX control */
70 /* PHY TX control word */
94 u8 phy_stat; /* PHY TX status */
134 __le16 phy_status0; /* PHY RX Status 0 */
135 __u8 jssi; /* PHY RX Status 1: JSSI */
136 __u8 sig_qual; /* PHY RX Status 1: Signal Quality */
137 PAD_BYTES(2); /* PHY RX Status 2 */
138 __le16 phy_status3; /* PHY RX Status 3 */
145 /* PHY RX Status 0 */
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/Linux-v5.4/drivers/net/ethernet/chelsio/cxgb3/
Dcommon.h2 * Copyright (c) 2005-2008 Chelsio, Inc. All rights reserved.
14 * - Redistributions of source code must retain the above
18 * - Redistributions in binary form must reproduce the above
44 #define CH_ERR(adap, fmt, ...) dev_err(&adap->pdev->dev, fmt, ##__VA_ARGS__)
45 #define CH_WARN(adap, fmt, ...) dev_warn(&adap->pdev->dev, fmt, ##__VA_ARGS__)
46 #define CH_ALERT(adap, fmt, ...) dev_alert(&adap->pdev->dev, fmt, ##__VA_ARGS__)
53 if ((adapter)->msg_enable & NETIF_MSG_##category) \
54 dev_printk(KERN_##level, &adapter->pdev->dev, fmt, \
92 enum { /* adapter interrupt-maintained statistics */
124 SGE_RXQ_PER_SET = 2, /* # of Rx queues per set */
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/Linux-v5.4/drivers/phy/qualcomm/
Dphy-qcom-ufs-i.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (c) 2013-2015, Linux Foundation. All rights reserved.
11 #include <linux/phy/phy.h>
76 * If UFS link is put into Hibern8 and if UFS PHY analog hardware is
78 * exit might fail even after powering on UFS PHY analog hardware.
80 * custom PHY settings just before PHY analog power collapse.
98 * struct ufs_qcom_phy_specific_ops - set of pointers to functions which have a
99 * specific implementation per phy. Each UFS phy, should implement
103 * checks pcs readiness. returns 0 for success and non-zero for error.
105 * @power_control: pointer to a function that controls analog rail of phy
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