| /Linux-v6.1/drivers/pinctrl/ |
| D | pinctrl-single.c | 210 #define PCS_QUIRK_HAS_SHARED_IRQ (pcs->flags & PCS_QUIRK_SHARED_IRQ)
211 #define PCS_HAS_IRQ (pcs->flags & PCS_FEAT_IRQ)
212 #define PCS_HAS_PINCONF (pcs->flags & PCS_FEAT_PINCONF)
273 static unsigned int pcs_pin_reg_offset_get(struct pcs_device *pcs, in pcs_pin_reg_offset_get() argument
276 unsigned int mux_bytes = pcs->width / BITS_PER_BYTE; in pcs_pin_reg_offset_get()
278 if (pcs->bits_per_mux) { in pcs_pin_reg_offset_get()
281 pin_offset_bytes = (pcs->bits_per_pin * pin) / BITS_PER_BYTE; in pcs_pin_reg_offset_get()
288 static unsigned int pcs_pin_shift_reg_get(struct pcs_device *pcs, in pcs_pin_shift_reg_get() argument
291 return (pin % (pcs->width / pcs->bits_per_pin)) * pcs->bits_per_pin; in pcs_pin_shift_reg_get()
298 struct pcs_device *pcs; in pcs_pin_dbg_show() local
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| /Linux-v6.1/drivers/net/ethernet/stmicro/stmmac/ |
| D | altr_tse_pcs.c | 62 static int tse_pcs_reset(void __iomem *base, struct tse_pcs *pcs) in tse_pcs_reset() argument
80 dev_err(pcs->dev, "PCS could not get out of sw reset\n"); in tse_pcs_reset()
87 int tse_pcs_init(void __iomem *base, struct tse_pcs *pcs) in tse_pcs_init() argument
98 ret = tse_pcs_reset(base, pcs); in tse_pcs_init()
101 pcs->sgmii_adapter_base + SGMII_ADAPTER_CTRL_REG); in tse_pcs_init()
106 static void pcs_link_timer_callback(struct tse_pcs *pcs) in pcs_link_timer_callback() argument
109 void __iomem *tse_pcs_base = pcs->tse_pcs_base; in pcs_link_timer_callback()
110 void __iomem *sgmii_adapter_base = pcs->sgmii_adapter_base; in pcs_link_timer_callback()
116 dev_dbg(pcs->dev, "Adapter: Link is established\n"); in pcs_link_timer_callback()
120 mod_timer(&pcs->aneg_link_timer, jiffies + in pcs_link_timer_callback()
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| D | dwmac-socfpga.c | 54 struct tse_pcs pcs; member
62 void __iomem *sgmii_adapter_base = dwmac->pcs.sgmii_adapter_base; in socfpga_dwmac_fix_mac_speed()
95 tse_pcs_fix_mac_speed(&dwmac->pcs, phy_dev, speed); in socfpga_dwmac_fix_mac_speed()
186 dwmac->pcs.sgmii_adapter_base = in socfpga_dwmac_parse_data()
189 if (IS_ERR(dwmac->pcs.sgmii_adapter_base)) { in socfpga_dwmac_parse_data()
190 ret = PTR_ERR(dwmac->pcs.sgmii_adapter_base); in socfpga_dwmac_parse_data()
208 dwmac->pcs.tse_pcs_base = in socfpga_dwmac_parse_data()
211 if (IS_ERR(dwmac->pcs.tse_pcs_base)) { in socfpga_dwmac_parse_data()
212 ret = PTR_ERR(dwmac->pcs.tse_pcs_base); in socfpga_dwmac_parse_data()
314 if (tse_pcs_init(dwmac->pcs.tse_pcs_base, &dwmac->pcs) != 0) { in socfpga_gen5_set_phy_mode()
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| /Linux-v6.1/drivers/net/pcs/ |
| D | pcs-lynx.c | 3 * Lynx PCS MDIO helpers
8 #include <linux/pcs-lynx.h>
10 #define SGMII_CLOCK_PERIOD_NS 8 /* PCS is clocked at 125 MHz */
26 struct phylink_pcs pcs; member
37 #define phylink_pcs_to_lynx(pl_pcs) container_of((pl_pcs), struct lynx_pcs, pcs)
38 #define lynx_to_phylink_pcs(lynx) (&(lynx)->pcs)
40 struct mdio_device *lynx_get_mdio_device(struct phylink_pcs *pcs) in lynx_get_mdio_device() argument
42 struct lynx_pcs *lynx = phylink_pcs_to_lynx(pcs); in lynx_get_mdio_device()
48 static void lynx_pcs_get_state_usxgmii(struct mdio_device *pcs, in lynx_pcs_get_state_usxgmii() argument
51 struct mii_bus *bus = pcs->bus; in lynx_pcs_get_state_usxgmii()
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| D | pcs-altera-tse.c | 11 #include <linux/pcs-altera-tse.h>
13 /* SGMII PCS register addresses
34 struct phylink_pcs pcs; member
39 static struct altera_tse_pcs *phylink_pcs_to_tse_pcs(struct phylink_pcs *pcs) in phylink_pcs_to_tse_pcs() argument
41 return container_of(pcs, struct altera_tse_pcs, pcs); in phylink_pcs_to_tse_pcs()
66 /* Reset PCS block */ in tse_pcs_reset()
80 static int alt_tse_pcs_validate(struct phylink_pcs *pcs, in alt_tse_pcs_validate() argument
91 static int alt_tse_pcs_config(struct phylink_pcs *pcs, unsigned int mode, in alt_tse_pcs_config() argument
96 struct altera_tse_pcs *tse_pcs = phylink_pcs_to_tse_pcs(pcs); in alt_tse_pcs_config()
121 static void alt_tse_pcs_get_state(struct phylink_pcs *pcs, in alt_tse_pcs_get_state() argument
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| D | Makefile | 2 # Makefile for Linux PCS drivers
4 pcs_xpcs-$(CONFIG_PCS_XPCS) := pcs-xpcs.o pcs-xpcs-nxp.o
7 obj-$(CONFIG_PCS_LYNX) += pcs-lynx.o
8 obj-$(CONFIG_PCS_RZN1_MIIC) += pcs-rzn1-miic.o
9 obj-$(CONFIG_PCS_ALTERA_TSE) += pcs-altera-tse.o
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| D | pcs-rzn1-miic.c | 13 #include <linux/pcs-rzn1-miic.h>
16 #include <dt-bindings/net/pcs-rzn1-miic.h>
139 * @pcs: PCS structure associated to the port
145 struct phylink_pcs pcs; member
150 static struct miic_port *phylink_pcs_to_miic_port(struct phylink_pcs *pcs) in phylink_pcs_to_miic_port() argument
152 return container_of(pcs, struct miic_port, pcs); in phylink_pcs_to_miic_port()
189 static int miic_config(struct phylink_pcs *pcs, unsigned int mode, in miic_config() argument
193 struct miic_port *miic_port = phylink_pcs_to_miic_port(pcs); in miic_config()
240 static void miic_link_up(struct phylink_pcs *pcs, unsigned int mode, in miic_link_up() argument
243 struct miic_port *miic_port = phylink_pcs_to_miic_port(pcs); in miic_link_up()
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| D | Kconfig | 3 # PCS Layer Configuration
6 menu "PCS device drivers"
18 This module provides helpers to phylink for managing the Lynx PCS
26 on RZ/N1 SoCs. This PCS converts MII to RMII/RGMII or can be set in
33 Ethernet SGMII PCS, that can be found on the Intel Socfpga family.
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| D | pcs-xpcs-nxp.c | 4 #include <linux/pcs/pcs-xpcs.h>
5 #include "pcs-xpcs.h"
67 /* In NXP SJA1105, the PCS is integrated with a PMA that has the TX lane
70 * PCS, via the DIGITAL_CONTROL_2 register.
126 /* Select PCS as transmitter data source. */ in nxp_sja1110_pma_config()
153 * Release reset of PMA to enable data flow to/from PCS. in nxp_sja1110_pma_config()
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| /Linux-v6.1/drivers/net/dsa/b53/ |
| D | b53_serdes.c | 20 static inline struct b53_pcs *pcs_to_b53_pcs(struct phylink_pcs *pcs) in pcs_to_b53_pcs() argument
22 return container_of(pcs, struct b53_pcs, pcs); in pcs_to_b53_pcs()
68 static int b53_serdes_config(struct phylink_pcs *pcs, unsigned int mode, in b53_serdes_config() argument
73 struct b53_device *dev = pcs_to_b53_pcs(pcs)->dev; in b53_serdes_config()
74 u8 lane = pcs_to_b53_pcs(pcs)->lane; in b53_serdes_config()
89 static void b53_serdes_an_restart(struct phylink_pcs *pcs) in b53_serdes_an_restart() argument
91 struct b53_device *dev = pcs_to_b53_pcs(pcs)->dev; in b53_serdes_an_restart()
92 u8 lane = pcs_to_b53_pcs(pcs)->lane; in b53_serdes_an_restart()
102 static void b53_serdes_get_state(struct phylink_pcs *pcs, in b53_serdes_get_state() argument
105 struct b53_device *dev = pcs_to_b53_pcs(pcs)->dev; in b53_serdes_get_state()
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| /Linux-v6.1/drivers/net/ethernet/mediatek/ |
| D | mtk_sgmii.c | 17 static struct mtk_pcs *pcs_to_mtk_pcs(struct phylink_pcs *pcs) in pcs_to_mtk_pcs() argument
19 return container_of(pcs, struct mtk_pcs, pcs); in pcs_to_mtk_pcs()
80 static int mtk_pcs_config(struct phylink_pcs *pcs, unsigned int mode, in mtk_pcs_config() argument
85 struct mtk_pcs *mpcs = pcs_to_mtk_pcs(pcs); in mtk_pcs_config()
97 static void mtk_pcs_restart_an(struct phylink_pcs *pcs) in mtk_pcs_restart_an() argument
99 struct mtk_pcs *mpcs = pcs_to_mtk_pcs(pcs); in mtk_pcs_restart_an()
107 static void mtk_pcs_link_up(struct phylink_pcs *pcs, unsigned int mode, in mtk_pcs_link_up() argument
110 struct mtk_pcs *mpcs = pcs_to_mtk_pcs(pcs); in mtk_pcs_link_up()
141 ss->pcs[i].ana_rgc3 = ana_rgc3; in mtk_sgmii_init()
142 ss->pcs[i].regmap = syscon_node_to_regmap(np); in mtk_sgmii_init()
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| /Linux-v6.1/include/linux/ |
| D | phylink.h | 126 * @ovr_an_inband: if true, override PCS to MLO_AN_INBAND
130 * are supported by the MAC/PCS.
149 * @mac_select_pcs: Select a PCS for the interface mode.
214 * mac_select_pcs: Select a PCS for the interface mode.
216 * @interface: PHY interface mode for PCS
221 * This must not modify any state. It is used to query which PCS should
224 * set the PCS that will be used.
234 * Read the current inband link state from the MAC PCS, reporting the
243 * PCS attached.
285 * in their &phylnk_config and which don't have a PCS), this function will be
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| /Linux-v6.1/drivers/phy/qualcomm/ |
| D | phy-qcom-qmp.h | 26 #include "phy-qcom-qmp-pcs-v2.h"
28 #include "phy-qcom-qmp-pcs-v3.h"
29 #include "phy-qcom-qmp-pcs-misc-v3.h"
30 #include "phy-qcom-qmp-pcs-ufs-v3.h"
32 #include "phy-qcom-qmp-pcs-v4.h"
33 #include "phy-qcom-qmp-pcs-pcie-v4.h"
34 #include "phy-qcom-qmp-pcs-usb-v4.h"
35 #include "phy-qcom-qmp-pcs-ufs-v4.h"
37 #include "phy-qcom-qmp-pcs-v4_20.h"
38 #include "phy-qcom-qmp-pcs-pcie-v4_20.h"
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| D | phy-qcom-qmp-combo.c | 108 /* PCS registers */
821 /* Init sequence for PHY blocks - serdes, tx, rx, pcs */
879 /* Offset from PCS to PCS_USB region */
897 * @pcs: iomapped memory space for lane's pcs
915 void __iomem *pcs; member
1426 qphy->pcs + QSERDES_DP_PHY_PD_CTL); in qcom_qmp_v3_phy_dp_aux_init()
1433 writel(DP_PHY_PD_CTL_PSR_PWRDN, qphy->pcs + QSERDES_DP_PHY_PD_CTL); in qcom_qmp_v3_phy_dp_aux_init()
1439 qphy->pcs + QSERDES_DP_PHY_PD_CTL); in qcom_qmp_v3_phy_dp_aux_init()
1447 writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG0); in qcom_qmp_v3_phy_dp_aux_init()
1448 writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1); in qcom_qmp_v3_phy_dp_aux_init()
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| D | phy-qcom-qmp-pcie-msm8996.c | 90 /* PCS registers */
192 /* Init sequence for PHY blocks - serdes, tx, rx, pcs */
236 * @pcs: iomapped memory space for lane's pcs
248 void __iomem *pcs; member
515 void __iomem *pcs = qphy->pcs; in qmp_pcie_msm8996_power_on() local
535 /* Tx, Rx, and PCS configurations */ in qmp_pcie_msm8996_power_on()
542 qmp_pcie_msm8996_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num); in qmp_pcie_msm8996_power_on()
548 qphy_setbits(pcs, QPHY_V2_PCS_POWER_DOWN_CONTROL, cfg->pwrdn_ctrl); in qmp_pcie_msm8996_power_on()
554 qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); in qmp_pcie_msm8996_power_on()
557 qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl); in qmp_pcie_msm8996_power_on()
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| /Linux-v6.1/Documentation/devicetree/bindings/net/ |
| D | nvidia,tegra234-mgbe.yaml | 49 - const: eee-pcs
50 - const: rx-pcs-input
51 - const: rx-pcs-m
52 - const: rx-pcs
53 - const: tx-pcs
61 - const: pcs
137 "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m",
138 "rx-pcs", "tx-pcs";
141 reset-names = "mac", "pcs";
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| D | xilinx_axienet.txt | 30 this to the PCS/PMA PHY is deprecated and should be avoided.
52 PCS/PMA PHY)
72 - pcs-handle: Phandle to the internal PCS/PMA PHY in SGMII or 1000Base-X
73 modes, where "pcs-handle" should be used to point
74 to the PCS/PMA PHY, and "phy-handle" should point to an
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| /Linux-v6.1/drivers/gpu/drm/amd/amdgpu/ |
| D | amdgpu_xgmi.c | 88 {"XGMI PCS DataLossErr",
90 {"XGMI PCS TrainingErr",
92 {"XGMI PCS CRCErr",
94 {"XGMI PCS BERExceededErr",
96 {"XGMI PCS TxMetaDataErr",
98 {"XGMI PCS ReplayBufParityErr",
100 {"XGMI PCS DataParityErr",
102 {"XGMI PCS ReplayFifoOverflowErr",
104 {"XGMI PCS ReplayFifoUnderflowErr",
106 {"XGMI PCS ElasticFifoOverflowErr",
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| /Linux-v6.1/drivers/net/ethernet/microchip/lan966x/ |
| D | lan966x_phylink.c | 78 /* Take PCS out of reset */ in lan966x_phylink_mac_link_down()
86 static struct lan966x_port *lan966x_pcs_to_port(struct phylink_pcs *pcs) in lan966x_pcs_to_port() argument
88 return container_of(pcs, struct lan966x_port, phylink_pcs); in lan966x_pcs_to_port()
91 static void lan966x_pcs_get_state(struct phylink_pcs *pcs, in lan966x_pcs_get_state() argument
94 struct lan966x_port *port = lan966x_pcs_to_port(pcs); in lan966x_pcs_get_state()
99 static int lan966x_pcs_config(struct phylink_pcs *pcs, in lan966x_pcs_config() argument
105 struct lan966x_port *port = lan966x_pcs_to_port(pcs); in lan966x_pcs_config()
117 netdev_err(port->dev, "port PCS config failed: %d\n", ret); in lan966x_pcs_config()
122 static void lan966x_pcs_aneg_restart(struct phylink_pcs *pcs) in lan966x_pcs_aneg_restart() argument
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| /Linux-v6.1/drivers/net/ethernet/microchip/sparx5/ |
| D | sparx5_phylink.c | 75 static struct sparx5_port *sparx5_pcs_to_port(struct phylink_pcs *pcs) in sparx5_pcs_to_port() argument
77 return container_of(pcs, struct sparx5_port, phylink_pcs); in sparx5_pcs_to_port()
80 static void sparx5_pcs_get_state(struct phylink_pcs *pcs, in sparx5_pcs_get_state() argument
83 struct sparx5_port *port = sparx5_pcs_to_port(pcs); in sparx5_pcs_get_state()
94 static int sparx5_pcs_config(struct phylink_pcs *pcs, in sparx5_pcs_config() argument
100 struct sparx5_port *port = sparx5_pcs_to_port(pcs); in sparx5_pcs_config()
122 /* Enable the PCS matching this interface type */ in sparx5_pcs_config()
125 netdev_err(port->ndev, "port PCS config failed: %d\n", ret); in sparx5_pcs_config()
129 static void sparx5_pcs_aneg_restart(struct phylink_pcs *pcs) in sparx5_pcs_aneg_restart() argument
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| /Linux-v6.1/drivers/clocksource/ |
| D | timer-pistachio.c | 70 struct pistachio_clocksource *pcs = to_pistachio_clocksource(cs); in pistachio_clocksource_read_cycles() local
80 raw_spin_lock_irqsave(&pcs->lock, flags); in pistachio_clocksource_read_cycles()
81 overflow = gpt_readl(pcs->base, TIMER_CURRENT_OVERFLOW_VALUE, 0); in pistachio_clocksource_read_cycles()
82 counter = gpt_readl(pcs->base, TIMER_CURRENT_VALUE, 0); in pistachio_clocksource_read_cycles()
83 raw_spin_unlock_irqrestore(&pcs->lock, flags); in pistachio_clocksource_read_cycles()
96 struct pistachio_clocksource *pcs = to_pistachio_clocksource(cs); in pistachio_clksrc_set_mode() local
99 val = gpt_readl(pcs->base, TIMER_CFG, timeridx); in pistachio_clksrc_set_mode()
105 gpt_writel(pcs->base, val, TIMER_CFG, timeridx); in pistachio_clksrc_set_mode()
110 struct pistachio_clocksource *pcs = to_pistachio_clocksource(cs); in pistachio_clksrc_enable() local
114 gpt_writel(pcs->base, RELOAD_VALUE, TIMER_RELOAD_VALUE, timeridx); in pistachio_clksrc_enable()
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| /Linux-v6.1/arch/arm64/boot/dts/freescale/ |
| D | fsl-ls1088a-rdb.dts | 23 pcs-handle = <&pcs2>;
30 pcs-handle = <&pcs3_0>;
37 pcs-handle = <&pcs3_1>;
44 pcs-handle = <&pcs3_2>;
51 pcs-handle = <&pcs3_3>;
58 pcs-handle = <&pcs7_0>;
65 pcs-handle = <&pcs7_1>;
72 pcs-handle = <&pcs7_2>;
79 pcs-handle = <&pcs7_3>;
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| D | fsl-ls1088a-ten64.dts | 95 pcs-handle = <&pcs1>;
103 pcs-handle = <&pcs2>;
113 pcs-handle = <&pcs3_0>;
120 pcs-handle = <&pcs3_1>;
127 pcs-handle = <&pcs3_2>;
134 pcs-handle = <&pcs3_3>;
142 pcs-handle = <&pcs7_0>;
149 pcs-handle = <&pcs7_1>;
156 pcs-handle = <&pcs7_2>;
163 pcs-handle = <&pcs7_3>;
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| /Linux-v6.1/drivers/net/phy/ |
| D | phylink.c | 47 struct phylink_pcs *pcs; member
597 struct phylink_pcs *pcs; in phylink_validate_mac_and_pcs() local
600 /* Get the PCS for this interface mode */ in phylink_validate_mac_and_pcs()
602 pcs = pl->mac_ops->mac_select_pcs(pl->config, state->interface); in phylink_validate_mac_and_pcs()
603 if (IS_ERR(pcs)) in phylink_validate_mac_and_pcs()
604 return PTR_ERR(pcs); in phylink_validate_mac_and_pcs()
606 pcs = pl->pcs; in phylink_validate_mac_and_pcs()
609 if (pcs) { in phylink_validate_mac_and_pcs()
610 /* The PCS, if present, must be setup before phylink_create() in phylink_validate_mac_and_pcs()
614 if (!pcs->ops) { in phylink_validate_mac_and_pcs()
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| /Linux-v6.1/arch/mips/cavium-octeon/executive/ |
| D | cvmx-helper-sgmii.c | 65 * Write PCS*_LINK*_TIMER_COUNT_REG[COUNT] with the in __cvmx_helper_sgmii_hardware_init_one_time()
88 * 1000BASE-X mode, tx_Config_Reg<D15:D0> is PCS*_AN*_ADV_REG. in __cvmx_helper_sgmii_hardware_init_one_time()
90 * PCS*_SGM*_AN_ADV_REG. In SGMII MAC mode, in __cvmx_helper_sgmii_hardware_init_one_time()
142 * Take PCS through a reset sequence. in __cvmx_helper_sgmii_hardware_init_link()
143 * PCS*_MR*_CONTROL_REG[PWR_DN] should be cleared to zero. in __cvmx_helper_sgmii_hardware_init_link()
144 * Write PCS*_MR*_CONTROL_REG[RESET]=1 (while not changing the in __cvmx_helper_sgmii_hardware_init_link()
145 * value of the other PCS*_MR*_CONTROL_REG bits). Read in __cvmx_helper_sgmii_hardware_init_link()
146 * PCS*_MR*_CONTROL_REG[RESET] until it changes value to in __cvmx_helper_sgmii_hardware_init_link()
166 * Write PCS*_MR*_CONTROL_REG[RST_AN]=1 to ensure a fresh in __cvmx_helper_sgmii_hardware_init_link()
176 * Wait for PCS*_MR*_STATUS_REG[AN_CPT] to be set, indicating in __cvmx_helper_sgmii_hardware_init_link()
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