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/Linux-v5.15/drivers/clk/
Dclk-xgene.c445 struct xgene_clk *pclk = to_xgene_clk(hw); in xgene_clk_enable() local
449 if (pclk->lock) in xgene_clk_enable()
450 spin_lock_irqsave(pclk->lock, flags); in xgene_clk_enable()
452 if (pclk->param.csr_reg) { in xgene_clk_enable()
455 data = xgene_clk_read(pclk->param.csr_reg + in xgene_clk_enable()
456 pclk->param.reg_clk_offset); in xgene_clk_enable()
457 data |= pclk->param.reg_clk_mask; in xgene_clk_enable()
458 xgene_clk_write(data, pclk->param.csr_reg + in xgene_clk_enable()
459 pclk->param.reg_clk_offset); in xgene_clk_enable()
462 pclk->param.reg_clk_offset, pclk->param.reg_clk_mask, in xgene_clk_enable()
[all …]
Dclk-stm32mp1.c1354 #define PCLK(_id, _name, _parent, _flags, _mgate)\ macro
1855 PCLK(TIM2, "tim2", "pclk1", CLK_IGNORE_UNUSED, G_TIM2),
1856 PCLK(TIM3, "tim3", "pclk1", CLK_IGNORE_UNUSED, G_TIM3),
1857 PCLK(TIM4, "tim4", "pclk1", CLK_IGNORE_UNUSED, G_TIM4),
1858 PCLK(TIM5, "tim5", "pclk1", CLK_IGNORE_UNUSED, G_TIM5),
1859 PCLK(TIM6, "tim6", "pclk1", CLK_IGNORE_UNUSED, G_TIM6),
1860 PCLK(TIM7, "tim7", "pclk1", CLK_IGNORE_UNUSED, G_TIM7),
1861 PCLK(TIM12, "tim12", "pclk1", CLK_IGNORE_UNUSED, G_TIM12),
1862 PCLK(TIM13, "tim13", "pclk1", CLK_IGNORE_UNUSED, G_TIM13),
1863 PCLK(TIM14, "tim14", "pclk1", CLK_IGNORE_UNUSED, G_TIM14),
[all …]
Dclk-conf.c18 struct clk *clk, *pclk; in __set_clk_parents() local
38 pclk = of_clk_get_from_provider(&clkspec); in __set_clk_parents()
39 if (IS_ERR(pclk)) { in __set_clk_parents()
40 if (PTR_ERR(pclk) != -EPROBE_DEFER) in __set_clk_parents()
43 return PTR_ERR(pclk); in __set_clk_parents()
63 rc = clk_set_parent(clk, pclk); in __set_clk_parents()
66 __clk_get_name(clk), __clk_get_name(pclk), rc); in __set_clk_parents()
68 clk_put(pclk); in __set_clk_parents()
72 clk_put(pclk); in __set_clk_parents()
/Linux-v5.15/drivers/clk/x86/
Dclk-pmc-atom.c165 struct clk_plt *pclk; in plt_clk_register() local
169 pclk = devm_kzalloc(&pdev->dev, sizeof(*pclk), GFP_KERNEL); in plt_clk_register()
170 if (!pclk) in plt_clk_register()
179 pclk->hw.init = &init; in plt_clk_register()
180 pclk->reg = pmc_data->base + PMC_CLK_CTL_OFFSET + id * PMC_CLK_CTL_SIZE; in plt_clk_register()
181 spin_lock_init(&pclk->lock); in plt_clk_register()
188 if (pmc_data->critical && plt_clk_is_enabled(&pclk->hw)) in plt_clk_register()
191 ret = devm_clk_hw_register(&pdev->dev, &pclk->hw); in plt_clk_register()
193 pclk = ERR_PTR(ret); in plt_clk_register()
197 pclk->lookup = clkdev_hw_create(&pclk->hw, init.name, NULL); in plt_clk_register()
[all …]
/Linux-v5.15/drivers/clocksource/
Dtimer-microchip-pit64b.c53 * @pclk: PIT64B's peripheral clock
59 struct clk *pclk; member
138 clk_disable_unprepare(timer->pclk); in mchp_pit64b_suspend()
143 clk_prepare_enable(timer->pclk); in mchp_pit64b_resume()
249 * PIT64B timer may be fed by gclk or pclk. When gclk is used its rate has to
250 * be at least 3 times lower that pclk's rate. pclk rate is fixed, gclk rate
251 * could be changed via clock APIs. The chosen clock (pclk or gclk) could be
256 * requested rate. If PCLK/GCLK < 3 (condition requested by PIT64B hardware)
257 * then the function falls back on using PCLK as clock source for PIT64B timer
268 * | |-->pclk -->|-->| | +---------+ +-----+ |
[all …]
Dtimer-rockchip.c37 struct clk *pclk; member
131 struct clk *pclk; in rk_timer_probe() local
146 pclk = of_clk_get_by_name(np, "pclk"); in rk_timer_probe()
147 if (IS_ERR(pclk)) { in rk_timer_probe()
148 ret = PTR_ERR(pclk); in rk_timer_probe()
149 pr_err("Failed to get pclk for '%s'\n", TIMER_NAME); in rk_timer_probe()
153 ret = clk_prepare_enable(pclk); in rk_timer_probe()
155 pr_err("Failed to enable pclk for '%s'\n", TIMER_NAME); in rk_timer_probe()
158 timer->pclk = pclk; in rk_timer_probe()
191 clk_disable_unprepare(pclk); in rk_timer_probe()
[all …]
Ddw_apb_timer_of.c21 struct clk *pclk; in timer_get_base_and_rate() local
44 pclk = of_clk_get_by_name(np, "pclk"); in timer_get_base_and_rate()
45 if (!IS_ERR(pclk)) in timer_get_base_and_rate()
46 if (clk_prepare_enable(pclk)) in timer_get_base_and_rate()
47 pr_warn("pclk for %pOFn is present, but could not be activated\n", in timer_get_base_and_rate()
77 if (!IS_ERR(pclk)) { in timer_get_base_and_rate()
78 clk_disable_unprepare(pclk); in timer_get_base_and_rate()
79 clk_put(pclk); in timer_get_base_and_rate()
/Linux-v5.15/arch/arm/boot/dts/
Dversatile-ab.dts150 pclk: pclk@24M { label
225 clocks = <&pclk>;
233 clocks = <&xtal24mhz>, <&pclk>;
241 clocks = <&xtal24mhz>, <&pclk>;
249 clocks = <&xtal24mhz>, <&pclk>;
256 clocks = <&pclk>;
263 clocks = <&pclk>;
271 clocks = <&osc1>, <&pclk>;
310 clocks = <&pclk>;
318 clocks = <&pclk>;
[all …]
Decx-common.dtsi50 clocks = <&pclk>;
60 clocks = <&pclk>;
71 clocks = <&pclk>;
82 clocks = <&pclk>;
93 clocks = <&pclk>;
102 clocks = <&pclk>;
110 clocks = <&pclk>;
118 clocks = <&pclk>, <&pclk>;
187 pclk: pclk { label
199 clocks = <&pclk>;
Darm-realview-eb.dtsi111 pclk: pclk@0 { label
313 clocks = <&pclk>;
326 clocks = <&mclk>, <&pclk>;
336 clocks = <&kmiclk>, <&pclk>;
343 clocks = <&kmiclk>, <&pclk>;
350 clocks = <&pclk>;
357 clocks = <&uartclk>, <&pclk>;
364 clocks = <&uartclk>, <&pclk>;
371 clocks = <&uartclk>, <&pclk>;
378 clocks = <&uartclk>, <&pclk>;
[all …]
Darm-realview-pbx.dtsi126 pclk: pclk@0 { label
355 clocks = <&uartclk>, <&pclk>;
362 clocks = <&uartclk>, <&pclk>;
369 clocks = <&uartclk>, <&pclk>;
376 clocks = <&sspclk>, <&pclk>;
383 clocks = <&wdogclk>, <&pclk>;
391 clocks = <&wdogclk>, <&pclk>;
401 <&pclk>;
412 <&pclk>;
425 clocks = <&pclk>;
[all …]
Darm-realview-pb1176.dts113 pclk: pclk@0 { label
355 clocks = <&timclk>, <&timclk>, <&pclk>;
365 clocks = <&timclk>, <&timclk>, <&pclk>;
374 clocks = <&pclk>;
387 clocks = <&pclk>;
396 clocks = <&sspclk>, <&pclk>;
405 clocks = <&uartclk>, <&pclk>;
414 clocks = <&uartclk>, <&pclk>;
423 clocks = <&uartclk>, <&pclk>;
432 clocks = <&uartclk>, <&pclk>;
[all …]
Darm-realview-pb11mp.dts227 pclk: pclk@0 { label
458 clocks = <&pclk>;
473 clocks = <&mclk>, <&pclk>;
485 clocks = <&kmiclk>, <&pclk>;
494 clocks = <&kmiclk>, <&pclk>;
503 clocks = <&uartclk>, <&pclk>;
512 clocks = <&uartclk>, <&pclk>;
521 clocks = <&uartclk>, <&pclk>;
530 clocks = <&uartclk>, <&pclk>;
539 clocks = <&sspclk>, <&pclk>;
[all …]
Dste-nomadik-stn8815.dtsi40 clocks = <&timclk>, <&pclk>;
49 clocks = <&timclk>, <&pclk>;
64 clocks = <&pclk>;
78 clocks = <&pclk>;
92 clocks = <&pclk>;
107 clocks = <&pclk>;
232 /* The PCLK domain uses HCLK right off */
233 pclk: pclk@0 { label
332 clocks = <&pclk>;
338 clocks = <&pclk>;
[all …]
Dmeson6.dtsi52 clock-names = "xtal", "pclk";
57 clock-names = "xtal", "pclk", "baud";
62 clock-names = "xtal", "pclk", "baud";
67 clock-names = "xtal", "pclk", "baud";
72 clock-names = "xtal", "pclk", "baud";
/Linux-v5.15/drivers/clk/samsung/
Dclk-s3c64xx.c164 DIV(PCLK, "pclk", "hclkx2", CLK_DIV0, 12, 4),
221 GATE_ON(PCLK_SKEY, "pclk_skey", "pclk", PCLK_GATE, 24),
222 GATE_ON(PCLK_CHIPID, "pclk_chipid", "pclk", PCLK_GATE, 23),
223 GATE_BUS(PCLK_SPI1, "pclk_spi1", "pclk", PCLK_GATE, 22),
224 GATE_BUS(PCLK_SPI0, "pclk_spi0", "pclk", PCLK_GATE, 21),
225 GATE_BUS(PCLK_HSIRX, "pclk_hsirx", "pclk", PCLK_GATE, 20),
226 GATE_BUS(PCLK_HSITX, "pclk_hsitx", "pclk", PCLK_GATE, 19),
227 GATE_ON(PCLK_GPIO, "pclk_gpio", "pclk", PCLK_GATE, 18),
228 GATE_BUS(PCLK_IIC0, "pclk_iic0", "pclk", PCLK_GATE, 17),
229 GATE_BUS(PCLK_IIS1, "pclk_iis1", "pclk", PCLK_GATE, 16),
[all …]
Dclk-s3c2412.c63 DIV(PCLK, "pclk", "hclk", CLKDIVN, 2, 1),
106 GATE(PCLK_WDT, "wdt", "pclk", CLKCON, 28, 0, 0),
107 GATE(PCLK_SPI, "spi", "pclk", CLKCON, 27, 0, 0),
108 GATE(PCLK_I2S, "i2s", "pclk", CLKCON, 26, 0, 0),
109 GATE(PCLK_I2C, "i2c", "pclk", CLKCON, 25, 0, 0),
110 GATE(PCLK_ADC, "adc", "pclk", CLKCON, 24, 0, 0),
111 GATE(PCLK_RTC, "rtc", "pclk", CLKCON, 23, 0, 0),
112 GATE(PCLK_GPIO, "gpio", "pclk", CLKCON, 22, CLK_IGNORE_UNUSED, 0),
113 GATE(PCLK_UART2, "uart2", "pclk", CLKCON, 21, 0, 0),
114 GATE(PCLK_UART1, "uart1", "pclk", CLKCON, 20, 0, 0),
[all …]
Dclk-s3c2443.c102 DIV(PCLK, "pclk", "hclk", CLKDIV0, 2, 1),
130 GATE(PCLK_GPIO, "gpio", "pclk", PCLKCON, 13, CLK_IGNORE_UNUSED, 0),
131 GATE(PCLK_RTC, "rtc", "pclk", PCLKCON, 12, 0, 0),
132 GATE(PCLK_WDT, "wdt", "pclk", PCLKCON, 11, 0, 0),
133 GATE(PCLK_PWM, "pwm", "pclk", PCLKCON, 10, 0, 0),
134 GATE(PCLK_I2S0, "i2s0", "pclk", PCLKCON, 9, 0, 0),
135 GATE(PCLK_AC97, "ac97", "pclk", PCLKCON, 8, 0, 0),
136 GATE(PCLK_ADC, "adc", "pclk", PCLKCON, 7, 0, 0),
137 GATE(PCLK_SPI0, "spi0", "pclk", PCLKCON, 6, 0, 0),
138 GATE(PCLK_I2C0, "i2c0", "pclk", PCLKCON, 4, 0, 0),
[all …]
/Linux-v5.15/drivers/clk/hisilicon/
Dclk-hi3620.c35 static const char *const uart0_mux_p[] __initconst = { "osc26m", "pclk", };
36 static const char *const uart1_mux_p[] __initconst = { "osc26m", "pclk", };
37 static const char *const uart2_mux_p[] __initconst = { "osc26m", "pclk", };
38 static const char *const uart3_mux_p[] __initconst = { "osc26m", "pclk", };
39 static const char *const uart4_mux_p[] __initconst = { "osc26m", "pclk", };
69 { HI3620_PCLK, "pclk", NULL, 0, 26000000, },
138 { HI3620_RTCCLK, "rtcclk", "pclk", CLK_SET_RATE_PARENT, 0x20, 5, 0, },
139 { HI3620_KPC_CLK, "kpc_clk", "pclk", CLK_SET_RATE_PARENT, 0x20, 6, 0, },
140 { HI3620_GPIOCLK0, "gpioclk0", "pclk", CLK_SET_RATE_PARENT, 0x20, 8, 0, },
141 { HI3620_GPIOCLK1, "gpioclk1", "pclk", CLK_SET_RATE_PARENT, 0x20, 9, 0, },
[all …]
/Linux-v5.15/drivers/iio/dac/
Dstm32-dac-core.c22 * @pclk: peripheral clock common for all DACs
27 struct clk *pclk; member
64 ret = clk_prepare_enable(priv->pclk); in stm32_dac_core_hw_start()
66 dev_err(dev, "pclk enable failed: %d\n", ret); in stm32_dac_core_hw_start()
83 clk_disable_unprepare(priv->pclk); in stm32_dac_core_hw_stop()
114 regmap = devm_regmap_init_mmio_clk(dev, "pclk", mmio, in stm32_dac_probe()
120 priv->pclk = devm_clk_get(dev, "pclk"); in stm32_dac_probe()
121 if (IS_ERR(priv->pclk)) { in stm32_dac_probe()
122 ret = PTR_ERR(priv->pclk); in stm32_dac_probe()
123 dev_err(dev, "pclk get failed\n"); in stm32_dac_probe()
[all …]
/Linux-v5.15/drivers/cpufreq/
Ds3c2410-cpufreq.c45 unsigned long hclk, fclk, pclk; in s3c2410_cpufreq_calcdivs() local
65 pdiv = (hclk > cfg->max.pclk) ? 2 : 1; in s3c2410_cpufreq_calcdivs()
66 pclk = hclk / pdiv; in s3c2410_cpufreq_calcdivs()
68 if (pclk > cfg->max.pclk) { in s3c2410_cpufreq_calcdivs()
69 s3c_freq_dbg("%s: pclk too big\n", __func__); in s3c2410_cpufreq_calcdivs()
86 .pclk = 50000000,
139 s3c2410_cpufreq_info.max.pclk = 66500000; in s3c2410a_cpufreq_add()
/Linux-v5.15/sound/soc/meson/
Daiu.c86 return clk_prepare_enable(aiu->i2s.clks[PCLK].clk); in aiu_cpu_component_probe()
93 clk_disable_unprepare(aiu->i2s.clks[PCLK].clk); in aiu_cpu_component_remove()
203 [PCLK] = "i2s_pclk",
210 [PCLK] = "spdif_pclk",
220 aiu->pclk = devm_clk_get(dev, "pclk"); in aiu_clk_get()
221 if (IS_ERR(aiu->pclk)) { in aiu_clk_get()
222 if (PTR_ERR(aiu->pclk) != -EPROBE_DEFER) in aiu_clk_get()
223 dev_err(dev, "Can't get the aiu pclk\n"); in aiu_clk_get()
224 return PTR_ERR(aiu->pclk); in aiu_clk_get()
250 ret = clk_prepare_enable(aiu->pclk); in aiu_clk_get()
[all …]
/Linux-v5.15/drivers/pwm/
Dpwm-rockchip.c35 struct clk *pclk; member
71 ret = clk_enable(pc->pclk); in rockchip_pwm_get_state()
98 clk_disable(pc->pclk); in rockchip_pwm_get_state()
193 ret = clk_enable(pc->pclk); in rockchip_pwm_apply()
221 clk_disable(pc->pclk); in rockchip_pwm_apply()
327 pc->pclk = devm_clk_get(&pdev->dev, "pclk"); in rockchip_pwm_probe()
329 pc->pclk = pc->clk; in rockchip_pwm_probe()
331 if (IS_ERR(pc->pclk)) { in rockchip_pwm_probe()
332 ret = PTR_ERR(pc->pclk); in rockchip_pwm_probe()
344 ret = clk_prepare_enable(pc->pclk); in rockchip_pwm_probe()
[all …]
/Linux-v5.15/drivers/rtc/
Drtc-ftrtc010.c34 struct clk *pclk; member
123 rtc->pclk = devm_clk_get(dev, "PCLK"); in ftrtc010_rtc_probe()
124 if (IS_ERR(rtc->pclk)) { in ftrtc010_rtc_probe()
125 dev_err(dev, "could not get PCLK\n"); in ftrtc010_rtc_probe()
127 ret = clk_prepare_enable(rtc->pclk); in ftrtc010_rtc_probe()
129 dev_err(dev, "failed to enable PCLK\n"); in ftrtc010_rtc_probe()
188 if (!IS_ERR(rtc->pclk)) in ftrtc010_rtc_remove()
189 clk_disable_unprepare(rtc->pclk); in ftrtc010_rtc_remove()
/Linux-v5.15/sound/soc/stm/
Dstm32_sai.c49 clk_disable_unprepare(sai->pclk); in stm32_sai_pclk_disable()
59 ret = clk_prepare_enable(sai->pclk); in stm32_sai_pclk_enable()
175 sai->pclk = devm_clk_get(&pdev->dev, "pclk"); in stm32_sai_probe()
176 if (IS_ERR(sai->pclk)) { in stm32_sai_probe()
177 if (PTR_ERR(sai->pclk) != -EPROBE_DEFER) in stm32_sai_probe()
178 dev_err(&pdev->dev, "missing bus clock pclk: %ld\n", in stm32_sai_probe()
179 PTR_ERR(sai->pclk)); in stm32_sai_probe()
180 return PTR_ERR(sai->pclk); in stm32_sai_probe()
218 ret = clk_prepare_enable(sai->pclk); in stm32_sai_probe()
239 clk_disable_unprepare(sai->pclk); in stm32_sai_probe()

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